DM74ALS576A 반도체 회로 부품 판매점
Octal D-Type Edge-Triggered Flip-Flop with 3-STATE Outputs
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 Fairchild Semiconductor |
October 1986
Revised February 2000
DM74ALS576A
Octal D-Type Edge-Triggered Flip-Flop
with 3-STATE Outputs
General Description
These 8-bit registers feature totem-pole 3-STATE outputs
designed specifically for driving highly-capacitive or rela-
tively low-impedance loads. The high-impedance state and
increased high-logic-level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for inter-
face or pull-up components. They are particularly attractive
for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight flip-flops of the DM74ALS576A are edge-trig-
gered inverting D-type flip-flops. On the positive transition
of the clock, the Q outputs will be set to the complement of
the logic states that were set up at the D inputs.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (HIGH or LOW
logic levels) or a high-impedance state. In the high-imped-
ance state the outputs neither load nor drive the bus lines
significantly.
The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are OFF.
Features
s Switching specifications at 50 pF
s Switching specifications guaranteed over full tempera-
ture and VCC range
s Advanced oxide-isolated, ion-implanted Schottky TTL
process
s 3-STATE buffer-type outputs drive bus lines directly
Ordering Code:
Order Number Package Number
Package Description
DM74ALS576AWM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74ALS576AN
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
© 2000 Fairchild Semiconductor Corporation DS006228
www.fairchildsemi.com
Function Table
Output
Control
L
L
L
H
Clock
↑
↑
L
X
L = LOW State
H = HIGH State
X = Don’t Care
↑ = Positive Edge Transition
Z = High Impedance State
Q0 = Previous Condition of Q
D Output
Q
HL
LH
X Q0
XZ
Logic Diagram
www.fairchildsemi.com
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DM74ALS576A flip-flop
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DM74ALS576A
Octal D-Type Edge-Triggered Flip-Flop with 3-STATE Outputs - Fairchild Semiconductor
