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DM74ALS374 반도체 회로 부품 판매점

Octal 3-STATE D-Type Edge-Triggered Flip-Flop



Fairchild Semiconductor 로고
Fairchild Semiconductor
DM74ALS374 데이터시트, 핀배열, 회로
September 1986
Revised February 2000
DM74ALS374
Octal 3-STATE D-Type Edge-Triggered Flip-Flop
General Description
This 8-bit register features totem-pole 3-STATE outputs
designed specifically for driving highly-capacitive or rela-
tively low-impedance loads. The high-impedance state and
increased high-logic-level drive provides this register with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for inter-
face or pull-up components. It is particularly attractive for
implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
The eight flip-flops of the DM74ALS374 are edge-triggered
D-type flip-flops. On the positive transition of the clock, the
Q outputs will be set to the logic states that were set up at
the D inputs.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (HIGH or LOW
logic levels) or a high-impedance state. In the high-imped-
ance state the outputs neither load nor drive the bus lines
significantly.
The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are OFF.
Features
s Switching specifications at 50 pF
s Switching specifications guaranteed over full
temperature and VCC range
s Advanced oxide-isolated, ion-implanted Schottky TTL
process
s Functionally and pin-for-pin compatible with LS TTL
counterpart
s Improved AC performance over DM74LS374 at approxi-
mately half the power
s 3-STATE buffer-type outputs drive bus lines directly
Ordering Code:
Order Number Package Number
Package Description
DM74ALS374WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74ALS374SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74ALS374N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
© 2000 Fairchild Semiconductor Corporation DS006113
www.fairchildsemi.com


DM74ALS374 데이터시트, 핀배열, 회로
Function Table
L = LOW State
H = HIGH State
X = Don’t Care
↑ = Positive Edge Transition
Z = High Impedance State
Q0 = Previous Condition of Q
Logic Diagram
Output
Control
L
L
L
H
Clock
L
X
D
Output
Q
HH
LL
X Q0
XZ
www.fairchildsemi.com
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DM74ALS374 flip-flop

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