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PDF 74HC73 Data sheet ( Hoja de datos )

Número de pieza 74HC73
Descripción Dual JK flip-flop
Fabricantes NXP Semiconductors　
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No Preview Available ! 74HC73 Hoja de datos, Descripción, Manual

74HC73
Dual JK flip-flop with reset; negative-edge trigger
Rev. 5 — 2 December 2015
Product data sheet
1. General description
The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP)
and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be
stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.
(nR) is asynchronous, when LOW it overrides the clock and data inputs, forcing the nQ
output LOW and the nQ output HIGH. Schmitt-trigger action in the clock input makes the
circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of
VCC.
2. Features and benefits
Low-power dissipation
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +80 C and from 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description
74HC73D
40 C to +125 C SO14
plastic small outline package; 14 leads; body width 3.9 mm
74HC73DB
40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body width
5.3 mm
74HC73PW
40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body
width 4.4 mm
Version
SOT108-1
SOT337-1
SOT402-1

1 page




74HC73 pdf
Nexperia
74HC73
Dual JK flip-flop with reset; negative-edge trigger
8. Recommended operating conditions
Table 5.
Symbol
VCC
VI
VO
Tamb
t/V
Recommended operating conditions
Parameter
Conditions
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
9. Static characteristics
Min Typ Max Unit
2.0 5.0 6.0 V
0 - VCC V
0 - VCC V
40 - +125 C
- - 625 ns/V
- 1.67 139 ns/V
- - 83 ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
VIH HIGH-level VCC = 2.0 V
input voltage VCC = 4.5 V
1.5 1.2 -
1.5
-
1.5
3.15 2.4 - 3.15 - 3.15
-V
-V
VCC = 6.0 V
4.2 3.2 -
4.2
-
4.2
-V
VIL
LOW-level
VCC = 2.0 V
input voltage VCC = 4.5 V
- 0.8 0.5
-
0.5
-
0.5 V
- 2.1 1.35 -
1.35
-
1.35 V
VCC = 6.0 V
- 2.8 1.8
-
1.8
-
1.8 V
VOH
HIGH-level
VI = VIH or VIL
output voltage IO = 20 A; VCC = 2.0 V
1.9 2.0 -
1.9
-
1.9
-V
IO = 20 A; VCC = 4.5 V
4.4 4.5 -
4.4
-
4.4
-V
IO = 20 A; VCC = 6.0 V
5.9 6.0 -
5.9
-
5.9
-V
IO = 4 mA; VCC = 4.5 V
3.98 4.32 - 3.84
-
3.7
-V
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34
-
5.2
-V
VOL LOW-level VI = VIH or VIL
output voltage IO = 20 A; VCC = 2.0 V
- 0 0.1
-
0.1
-
0.1 V
IO = 20 A; VCC = 4.5 V
- 0 0.1
-
0.1
-
0.1 V
IO = 20 A; VCC = 6.0 V
- 0 0.1
-
0.1
-
0.1 V
IO = 4 mA; VCC = 4.5 V
- 0.15 0.26 - 0.33 -
0.4 V
IO = 5.2 mA; VCC = 6.0 V
- 0.16 0.26 -
0.33
-
0.4 V
II input leakage VI = VCC or GND;
current
VCC = 6.0 V
- - 0.1 -
1.0
-
1.0 A
ICC supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
- - 4.0
-
40.0
-
80.0 A
CI input
capacitance
- 3.5 -
-
-
-
- pF
74HC73
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 2 December 2015
© Nexperia B.V. 2017. All rights reserved
5 of 16

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74HC73 arduino
Nexperia
74HC73
Dual JK flip-flop with reset; negative-edge trigger
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Fig 10. Package outline SOT337-1 (SSOP14)
74HC73
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 2 December 2015
© Nexperia B.V. 2017. All rights reserved
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