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PDF 54ABT377 Data sheet ( Hoja de datos )
| Número de pieza | 54ABT377 | |
| Descripción | Octal D-Type Flip-Flop | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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July 1998
54ABT377
Octal D-Type Flip-Flop with Clock Enable
General Description
The ’ABT377 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) input loads all flip-flops simultaneously, when the
Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
Features
n Clock enable for address and data synchronization
applications
n Eight edge-triggered D flip-flops
n Buffered common clock
n See ’ABT273 for master reset version
n See ’ABT373 for transparent latch version
n See ’ABT374 for TRI-STATE® version
n Output sink capability of 48 mA, source capability of
24 mA
n Guaranteed latchup protection
n High impedance glitch free bus loading during entire
power up and power down cycle
n Non-destructive hot insertion capability
n Disable time less than enable time to avoid bus
contention
n Standard Microcircuit Drawing (SMD) 5962-9314801
Ordering Code:
Military
54ABT377J-QML
54ABT377W-QML
54ABT377E-QML
Connection Diagram
Package
Number
J20A
W20A
E20A
Pin Assignment for
DIP and Cerpack
Package Description
20-Lead Ceramic Dual-In-Line
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier, Type C
Pin Assignment for LCC
DS100216-1
DS100216-11
Pin
Names
D0– D7
CE
CP
Q0– Q7
Description
Data Inputs
Clock Enable (Active LOW)
Clock Pulse Input
Data Outputs
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100216
www.national.com
1 page  
AC Loading
DS100216-4
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
DS100216-5
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
FIGURE 2. VM = 1.5V
Input Pulse Requirements
DS100216-6
Amplitude Rep. Rate
tw
3.0V
1 MHz 500 ns
tr
2.5 ns
tf
2.5 ns
FIGURE 3. Test Input Signal Requirements
FIGURE 6. Setup Time, Hold Time
and Recovery Time Waveforms
DS100216-9
DS100216-8
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
5
www.national.com
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 54ABT377.PDF ] | |
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