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NXP Semiconductors |
74HC1G08-Q100; 74HCT1G08-Q100
2-input AND gate
Rev. 2 — 16 August 2012
Product data sheet
1. General description
74HC1G08-Q100 and 74HCT1G08-Q100 are high-speed, Si-gate CMOS devices. They
provide a 2-input AND function.
The HC device has CMOS input switching levels and supply voltage range 2 V to 6 V.
The HCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V.
The standard output currents are half of those of the 74HC08-Q100 and 74HCT08-Q100.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Symmetrical output impedance
High noise immunity
Low power dissipation
Balanced propagation delays
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name Description
Version
74HC1G08GW-Q100
74HCT1G08GW-Q100
40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; SOT353-1
body width 1.25 mm
74HC1G08GV-Q100
40 C to +125 C SC-74A plastic surface-mounted package; 5 leads
SOT753
74HCT1G08GV-Q100
NXP Semiconductors
74HC1G08-Q100; 74HCT1G08-Q100
2-input AND gate
4. Marking
Table 2. Marking codes
Type number
74HC1G08GW-Q100
74HCT1G08GW-Q100
74HC1G08GV-Q100
74HCT1G08GV-Q100
Marking[1]
HE
TE
H08
T08
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1B
2A
Fig 1. Logic symbol
Y4
mna113
1
&4
2
mna114
Fig 2. IEC logic symbol
B
A
Fig 3. Logic diagram
6. Pinning information
6.1 Pinning
Y
mna115
Fig 4. Pin configuration
74HC1G08-Q100
74HCT1G08-Q100
B1
A2
5 VCC
GND 3
4Y
aaa-003473
74HC_HCT1G08_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 August 2012
© NXP B.V. 2012. All rights reserved.
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