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PDF ML145554 Data sheet ( Hoja de datos )
| Número de pieza | ML145554 | |
| Descripción | (ML145554 - ML145567) PCM Codec-Filter | |
| Fabricantes | LANSDALE Semiconductor | |
| Logotipo |  |
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ML145554 ML145564
ML145557 ML145567
PCM Codec–Filter
Legacy Device: Motorola MC145554, MC145557, MC145564, MC145567
The ML145554, ML145557, ML145564, and ML145567 are all per channel
PCM Codec–Filters. These devices perform the voice digitization and recon-
struction as well as the band limiting and smoothing required for PCM sys-
tems. They are designed to operate in both synchronous and asynchronous
applications and contain an on–chip precision voltage reference. The
ML145554 (Mu–Law) and ML145557 (A–Law) are general purpose devices
that are offered in 16–pin packages. The ML145564 (Mu–Law) and
ML145567 (A–Law), offered in 20–pin packages, add the capability of analog
loopback and push–pull power amplifiers with adjustable gain.
These devices have an input operational amplifier whose output is the input
to the encoder section. The encoder section immediately low–pass filters the
analog signal with an active R–C filter to eliminate very–high–frequency noise
from being modulated down to the pass band by the switched capacitor filter.
From the active R–C filter, the analog signal is converted to a differential sig-
nal. From this point, all analog signal processing is done differentially. This
allows processing of an analog signal that is twice the amplitude allowed by a
single–ended design, which reduces the significance of noise to both the invert-
ed and non–inverted signal paths. Another advantage of this differential design
is that noise injected via the power supplies is a common–mode signal that is
cancelled when the inverted and non–inverted signals are recombined. This
dramatically improves the power supply rejection ratio.
After the differential converter, a differential switched capacitor filter band-
passes the analog signal from 200 Hz to 3400 Hz before the signal is digitized-
by the differential compressing A/D converter.
The decoder accepts PCM data and expands it using a differential D/A con-
verter. The output of the D/A is low–pass filtered at 3400 Hz and sinX/X com-
pensated by a differential switched capacitor filter. The signal is then filtered
by an active R–C filter to eliminate the out–of–band energy of the switched
capacitor filter.
These PCM Codec–Filters accept both long–frame and short–frame industry
standard clock formats. They also maintain compatibility with Motorola’s fami-
ly of TSACs and MC3419/MC34120 SLIC products.
The ML145554/57/64/67 family of PCM Codec–Filters utilizes CMOS due
to its reliable low–power performance and proven capability for complex
analog/digital VLSI functions.
FEATURES
16
1
16
1
P DIP 16 = EP
PLASTIC DIP
CASE 648
ML145554/57
SOG 16 = -5P
SOG PACKAGE
CASE 751G
ML145554/57
20
1
20
1
P DIP 20 = RP
PLASTIC DIP
CASE 738
ML145564/67
SOG 20 = -6P
SOG PACKAGE
CASE 751D
ML145564/67
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
MOTOROLA
LANSDALE
P DIP 16
SO 16W
P DIP 16
SO 16W
P DIP 20
SO 20W
P DIP 20
SO 20W
MC145554P
MC145554DW
MC145557P
MC145557DW
MC145564P
MC145564DW
MC145567P
MC145567DW
ML145554EP
ML145554-5P
ML145557EP
ML145557-5P
ML145564RP
ML145564-6P
ML145567RP
ML145567-6P
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
ML145554/57(16–Pin Package)
• Fully Differential Analog Circuit Design for Lowest Noise
• Performance Specified for Extended Temperature Range of – 40 to + 85°C
• Transmit Band–Pass and Receive Low–Pass Filters On–Chip
• Active R–C Pre–Filtering and Post–Filtering
• Mu–Law Companding ML145554
• A–Law Companding ML145557
• On–Chip Precision Voltage Reference (2.5 V)
• Typical Power Dissipation of 40 mW, Power Down of 1.0 mW at ±5 V
ML145564/67(20–Pin Package) — All of the Features of the ML145554/57 Plus:
• Mu–Law Companding ML145564
• A–Law Companding ML145567
• Push–Pull Power Drivers with External Gain Adjust
• Analog Loopback
Page 1 of 18
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Issue A
1 page  
LANSDALE Semiconductor, Inc.
www.DataSheet4U.com
ML145554, ML145557, ML145564, ML145567
complementary outputs. The output of the second amplifier may be
internally connected to the input of the transmit anti–aliasing filter by
bringing the ANLB pin high. The power amplifiers can drive unbal-
anced 300 Ω loads or a balanced 600 Ω load; they may be powered
down independent of the rest of the chip by tying the VPI pin to
VBB.
MASTER CLOCKS
Since the codec–filter design has a single DAC architecture, only
one master clock is used. In normal operation (both frame syncs
clocking), the MCLKX is used as the master clock, regardless of
whether the MCLKR/PDN pin is clocking or low. The same is true if
the part is in transmit half–channel mode (FSX clocking, FSR held
low). But if the codec–filter is in the receive half–channel mode, with
FSR clocking and FSX held low, MCLKR is used for the internal
master clock if it is clocking; if MCLKR is low, then MCLKX is still
used for the internal master clock. Since only one of the master
clocks isused at any given time, they need not be synchronous.
The master clock frequency must be 1.536 MHz, 1.544 MHz, or
2.048 MHz. The frequency that the codec–filter expects depends
upon whether the part is a Mu–Law or an A–Law part, and on the
state of the BCLKR/CLKSEL pin.The allowable options are shown
In Table 1. When a level (rather than a clock) is provided for
BCLKR/CLKSEL, BCLKX is used as the bit clock for both transmit
and receive.
Table 1. Master Clock Frequency Determination
Master Clock Frequency Expected
BCLKR/CLKSEL
Clocked, 1, or Open
ML145554/64
1.536 MHz
1.544 MHz
ML145557/67
2.048 MHz
0
2.048 MHz
1.536 MHz
1.544 MHz
FRAME SYNCS AND DIGITAL I/O
These codec–filters can accommodate both of the industry standard
timing formats. The Long Frame Sync mode isused by Lansdale’s
ML145500 family of codec–filters and the UDLT family of digital
loop transceivers. The Short Frame Sync mode is compatible with the
IDL (Interchip Digital Link) serial format used in Motorola and
Lansdale’s ISDN family and by other companies in their telecommu-
nication devices. These codec–filters use the length of the transmit
frame sync (FSX) to determine the timing format for both transmit
and receive unless the part is operating in the receive half–channel
mode.
In the Long Frame Sync mode, the frame sync pulses must be at
least three bit clock periods long. The DX and TSX outputs are
enabled by the logical ANDing of FSX and BCLKX; when both are
high, the sign bit appears at the DX output. The next seven rising
edges of BCLKX clock out the remaining seven bits of the PCM
word. The DX and TSX outputs return to a high impedance state on
the falling edge of the eighth bit clock or the falling edge of FSX,
whichever comes later. The receive PCM word is clocked into DR on
the eight falling BCLKR edges following an FSR rising edge.
For Short Frame Sync operation, the frame sync pulses must be
one bit clock period long. On the first BCLKX rising edge after the
falling edge of BCLKX has latched FSX high, the DX and TSX out-
puts are enabled and the sign bit is presented on DX. The next seven
rising edges of BCLKX clock out the remaining seven bits of the
PCM word; on the eighth BCLKX falling edge, the DX and TSX
outputs return to a high impedance state. On the second falling
BCLKR edge following an FSR rising edge, the receive sign bit is
clocked into DR. The next seven BCLKR falling edges clock in the
remaining seven bits of the receive PCM word.
Table 2 shows the coding format of the transmit and receive PCM
words.
HALF–CHANNEL MODES
In addition to the normal full–duplex operating mode, these
codec–filters can operate in both transmit and receive half–channel
modes. Transmit half–channel mode is entered by holding FSR low.
The VFRO output goes to analog ground but remains in a low imped-
ance state (to facilitate a hybrid interface); PCM data at DR is
ignored. Holding FSX low while clocking FSR puts these devices in
the receive half–channel mode. In this state, the transmit input oper-
ational amplifier continues to operate, but the rest of the transmit cir-
cuitry is disabled; the DX and TSX outputs remain in a high imped-
ance state. MCLKR is used as the internal master clock if it is clock-
ing. If MCLKR is not clocking, then MCLKX is used for the internal
master clock, but in that case it should be synchronous with FSR. If
BCLKR is not clocking, BCLKX will be used for the receive data,
just as in the full–channel operating mode. In receive half–channel
mode only, the length ofthe FSR pulse is used to determine whether
Short Frame Sync or Long Frame Sync timing is used at DR.
POWER–DOWN
Holding both FSX and FSR low causes the part to go into the
power–down state. Power–down occurs approximately 2 ms after the
last frame sync pulse is received. An alternative way to put these
devices in power–down is to hold the MCLKR/PDN pin high. When
the chip is powered down, the DX, TSX, and GSX outputs are high
impedance, the VFRO, VPO–, and VPO+ operational amplifiers are
biased with a trickle current so that their respective outputs remain
stable at analog ground. To return the chip to the power–up state,
MCLKR/PDN must be low or clocking and at least one of the frame
sync pulses must be present. The DX and TSX outputs will remain in
a high–impedance state until the second FSX pulse after power–up.
Table 2. PCM Data Format
Level
+ Full Scale
Mu–Law (ML145554/64)
Sign Bit
Chord Bits
Step Bits
1
000
0000
A–Law (ML145557/67)
Sign Bit
Chord Bits
Step Bits
1
010
1010
+ Zero
1
111
1111
1
101
0101
– Zero
0
111
1111
0
101
0101
– Full Scale
0
000
0000
0
010
1010
Page 5 of 18
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Issue A
5 Page 
LANSDALE Semiconductor, Inc.
www.DataSheet4U.com
ML145554, ML145557, ML145564, ML145567
MCLKX
MCLKR
BCLKX
FSX
DX
th(BF)
12
tsu(FB)
tsu(BRM)
34
th(BFI)
tsu(MFB)
5 67
89
td(ZF)
td(ZF)
td(BD)
MSB CH1
CH2
CH3
ST1 ST2
td(ZC)
ST3 LSB
td(ZC)
BCLKR
FSR
DR
th(BF)
1
tsu(FB)
2
3
th(BFI)
4
5
67
89
tsu(DB)
th(BD)
MSB CH1
CH2 CH3 ST1 ST2
Figure 2. Long Frame Sync Timing
th(BD)
ST3 LSB
Page 11 of 18
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Issue A
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ML145554.PDF ] | |
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