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PDF BL1302A57S Data sheet ( Hoja de datos )
| Número de pieza | BL1302A57S | |
| Descripción | Monolithic serial interface compiler encoder / filter | |
| Fabricantes | SHANGHAI BELLING | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de BL1302A57S (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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BL1302A57/S
General Description
The BL1302A57/S is an A-law monolithic PCM Pin Assignment
CODEC/filter which has the A/D and D/A
conversion and a serial PCM interface. The device is
fabricated using the advanced double-poly nwell
CMOS process. It is pin compatible with TP3057.
The encode portion of each device consists of an
input gain adjust amplifier, an active RC pre-filter
which eliminates very high frequency noise prior to
entering a switched-capacitor band-pass filter that
rejects signals below 200 Hz and above 3400 Hz.
Also included are auto-zero circuitry and a
VBB
GNDA
VFRO
VCC
FSR
DR
BCLKR/CLKSEL
MCLKR/PDN
1
2
3
4
5
6
7
8
16 VFXI+
15 VFXI-
14 GSX
13 TSX
12 FS X
11 DX
10 BCLKX
9 MCLKX
companding coder which samples the filtered signal
and encodes it in the companded A-law PCM format.
The decode portion consists of an expanding
decoder, which reconstructs the
Analog signal from the companded A-law code, a low-pass filter which corrects for the sinx/x
response of the decoder output and rejects signals above 3400 Hz followed by a single-ended
power amplifier capable of driving low impedance loads. The device requires two 1.536 MHz,
1.544 MHz or 2.048 MHz transmit and receive master clocks, which may be asynchronous;
transmit and receive bit clocks , which may vary from 64 KHz to 2.048 MHz; and transmit and
receive frame sync pulses. The timing of the frame sync pulses and PCM data is compatible with
both industry standard formats.
.
Features
• Complete CODEC and filtering system (COMBO) including:
--- Transmit high-pass and low-pass filtering
--- Receive low-pass filter with sinx/x correction
--- Active RC noise filters
--- A-law compatible COder and DECoder
--- Internal precision voltage reference
--- Serial I/O interface
--- Internal auto-zero circuitry
• 16 pin DIP or SOP
• Designed for ITU application
http://www.belling.com.cn
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Total 17 Pages
8/28/2006
Wrote by 2006
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BL1302A57/S
• Long frame operation
To use the long frame mode, the frame sync pulse, FSx and FS R , must be three or more bit clock
periods long, with timing relationships specified in Figure 2. Based on the transmit frame sync,
FSx, the device will sense whether short or long frame sync pulse are being used. For 64 kHz
operation, the frame sync pulse must be kept low for a minimum of 160ns. The Dx tri-state
output buffer is enabled with the rising edge of FSx or the rising edge of BCLKx , whichever
comes later, and the first bit clocked out is the sign bit. The following seven BCLKx rising edges
clock out the remaining seven bits. The Dx output is disabled by the falling BCLKx edge
following the eighth rising edge, or by FSx going low, whichever comes later. A rising edge on
the receive frame sync pulse, FS R, will cause the PCM data at DR to be latched in on the next
eight falling edges of BCLK R (BCLKx if BCLKR is a fixed level ).
• Single channel operation
Keeping FSR input continuously low, the device enters into transmit channel operation, the
data at DR input will be ignored. Keeping FSX input continuously low, the device enters into
receive channel operation. The most part of transmit circuitry ceases to work, DX and TSX
output will be in high impedance. If MCLKR input is a clock, it is the internal master clock. If
MCLKR input is not a clock, MCLKX is the internal master clock, and MCLKX must be
synchronous with FSR. If BCLKR input is not a clock, BCLKX is the internal bit clock. In receive
channel operation, the length of FSR determines whether it is short or long frame.
• Switch of operation
See picture below, it is not recommended that the switching from both channels to receive only or
switching from receive channel only to transmit channel only.
transmit
receive
POWER
DOWN
both
• Transmit section
The transmit section input is an operational amplifier with provision for gain adjustment using
two external resistors. The low noise and wide bandwidth allow gains in excess of 20 dB across
the audio passband to be realized. The op amp drives a unity-gain filter consisting of RC active
pre-filter, followed by an eighth order switched-capacitor bandpass filter clocked at 256 kHz.
The output of this filter directly drives the encoder sample-and-hold circuit. The A/D is of
companding type according to A-law coding conventions. A built-in bandgap voltage reference is
used to provide an input overload of nominally 2.492V peak. The FSx frame pulse controls the
sampling of the filter output, and then the successive-approximation encoding cycle begins. The
8-bit code is then loaded into a buffer and shifted out through Dx at the next FSx pulse. The total
encoding delay will be approximately 165us (due to transmit filter) plus 125us (due to encoding
delay), which totals 290us. Any offset voltage due to the filters or comparator is cancelled by
sign bit integration.
http://www.belling.com.cn
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Total 17 Pages
8/28/2006
Wrote by 2006
5 Page 
GXAT
GXAV
GXRL
GRA
GRR
GRAT
GRAV
GRRL
BL1302A57/S
f=300Hz-3000Hz
-0.15
f=3300Hz
-0.35
f=3400Hz
-0.7
f=4000Hz
f=4600Hz and Up, Measure
Response from 0 Hz to 4000 Hz
Absolute Transmit Gain
Variation with Tempera-
Relative to GXA
-0.1
ture
Absolute Transmit Gain
Variation with Supply
Relative to GXA
-0.05
Voltage
Transmit Gain Variations
Sinusoidal Test Method
with Level
Reference Level=-10dBm0
VFxI+=-40dBm0 to +3dBm0
-0.2
VFxI+=-50dBm0 to-40dBm0
-0.4
Receive Gain, Absolute
VFxI+=-55dBm0 to-50dBm0
TA=25 0C,Vcc=5V,VBB=-5V
Input=Digital Code Se-
-1.2
quence for 0 dBm0 Signal at -0.25
1020 Hz
Receive Gain, Relative to f=0Hz to 3000 Hz
-0.15
GRA
f=3300Hz
-0.35
f=3400Hz
-0.7
f=4000Hz
Absolute Receive Gain
Variation with Tempera-
Relative to GRA
-0.1
ture
Absolute Receive Gain
Variation with Supply
Relative to GRA
-0.05
Voltage
Receive Gain Variations
Sinusoidal Test Method;
with Level
Reference Input PCM Code
Corresponds to an Ideally
Encoded PCM Level
0.15 dB
0.05 dB
0 dB
-14 dB
-32 dB
0.1 dB
0.05 dB
0.2 dB
0.4 dB
1.2 dB
0.25 dB
0.15 dB
0.05 dB
0 dB
-14 dB
0.1 dB
0.05 dB
http://www.belling.com.cn
- 11 -
Total 17 Pages
8/28/2006
Wrote by 2006
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet BL1302A57S.PDF ] | |
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