|
|
PDF UDA1320ATS Data sheet ( Hoja de datos )
| Número de pieza | UDA1320ATS | |
| Descripción | Low-cost stereo filter DAC | |
| Fabricantes | Philips | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de UDA1320ATS (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
|
No Preview Available !
INTEGRATED CIRCUITS
DATA SHEET
UDA1320ATS
Low-cost stereo filter DAC
Preliminary specification
Supersedes data of 1999 Oct 11
File under Integrated Circuits, IC01
2000 Jan 10
1 page  
Philips Semiconductors
Low-cost stereo filter DAC
Preliminary specification
UDA1320ATS
7 PINNING
SYMBOL
BCK
WS
DATAI
VDDD
VSSD
SYSCLK
APPSEL
APPL3
APPL2
APPL1
APPL0
VREF(DAC)
VDDA
VO(L)
VSSA
VO(R)
PIN DESCRIPTION
1 bit clock
2 word select
3 data input
4 digital power supply
5 digital ground
6 system clock: 256fs, 384fs, 512fs
7 application mode select
8 application pin 3
9 application pin 2
10 application pin 1
11 application pin 0
12 DAC reference voltage
13 analog supply voltage
14 left output voltage
15 analog ground
16 right output voltage
handbook, halfpage
BCK 1
16 VO(R)
WS 2
15 VSSA
DATAI 3
14 VO(L)
VDDD 4
13 VDDA
UDA1320A
VSSD 5
12 VREF(DAC)
SYSCLK 6
11 APPL0
APPSEL 7
10 APPL1
APPL3 8
9 APPL2
MGM817
Fig.2 Pin configuration.
8 FUNCTIONAL DESCRIPTION
8.1 System clock
The UDA1320ATS/N2 operates in slave mode only. This
means in all applications the system devices must provide
the system clock. The system frequency is selectable and
depends on the mode of operation.
The options are 256fs, 384fs and 512fs for the L3 mode
and 256fs plus 384fs for the static mode. The system clock
must be locked in frequency to the digital interface input
signals.
The UDA1320ATS/N2 supports sampling frequencies
from 16kHz up to 48kHz
8.2 Application modes
The application mode can be set with the tri-value
APPSEL pin, to L3 mode (APPSEL = VSSD) or to either of
two static modes (APPSEL = 0.5VDDD or
APPSEL = VDDD). See Table 1 for APPL0 to APPL3 pin
functions (active = HIGH).
Table 1 Selection modes via APPSEL (note 1)
PIN
VSSD
APPL0
APPL1
APPL2
APPL3
TEST
L3CLOCK
L3MODE
L3DATA
APPSEL
0.5VDDD
(384fs)
MUTE
DEEM
SF0
SF1
VDDD
(256fs)
MUTE
DEEM
SF0
SF1
For example, in static pin control mode, the output signal
can be soft muted by setting APPL0 HIGH. De-emphasis
can be switched on for 44.1 kHz by setting APPL1 HIGH.
APPL1 LOW will disable de-emphasis.
Note that when L3 interface is used, an L3 initialisation
must be done when the IC is powered up!
In L3 mode pin APPL0 must be set to LOW.
2000 Jan 10
5
5 Page 
Philips Semiconductors
Low-cost stereo filter DAC
Preliminary specification
UDA1320ATS
10 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
VDDD
VDDA
Txtal(max)
Tstg
Tamb
Ves
digital supply voltage
analog supply voltage
maximum crystal temperature
storage temperature
ambient temperature
electrostatic handling
CONDITIONS
note 1
note 1
note 2
note 3
MIN.
−
−
−
−65
−40
−3 000
−300
MAX.
5.0
5.0
150
+125
+85
+3 000
+300
UNIT
V
V
°C
°C
°C
V
V
Notes
1. All supply connections must be made to the same power supply.
2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor, except pin 14 which must be specified to
−2500V (MIN) and +2500V (MAX).
3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor.
11 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices.
12 QUALITY SPECIFICATION
In accordance with “SNW-FQ-611-E”. The number of the quality specification can be found in the “Quality Reference
Handbook”. The handbook can be ordered using the code 9397 750 00192.
13 THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
Rth(j-a)
thermal resistance from junction to ambient
CONDITIONS
in free air
VALUE
190
UNIT
K/W
2000 Jan 10
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet UDA1320ATS.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| UDA1320ATS | Low-cost stereo filter DAC | Philips |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |