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PDF ISL1561 Data sheet ( Hoja de datos )
| Número de pieza | ISL1561 | |
| Descripción | Fixed Gain Dual Port Class-G Differential xDSL Line Driver | |
| Fabricantes | Intersil | |
| Logotipo |  |
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Fixed Gain Dual Port Class-G Differential xDSL Line
Driver
ISL1561
The ISL1561 is a fixed gain dual port class-G differential
amplifier designed for driving full rate ADSL2+ and VDSL2
signals at very low power dissipation. The driver runs on a
single +14V power supply and internally generates higher
supply voltages when needed to enable power efficient
operation for high peak-to-average ratio (PAR) ADSL2+ and
VDSL2 signals.
In ADSL2+ mode of operation with full 19.8dBm transmit
signal power across 100Ω line load, each port consumes only
520mW of power, while with 19.5dBm VDSL2 8b profile a port
consumes 610mW of power. In VDSL2 17a mode of operation
with 14.5dBm transmit power, a port will consume 411mW of
power. These typical power consumption figures account for
receiver hybrid loading effects and transformer losses.
The ISL1561 provides two ports of wideband, current feedback
amplifiers optimized for low power consumption in xDSL
systems. The drivers achieve an average upstream missing
band power ratio (MBPR) distortion of better than -64dBc
under 19.8dBm transmit signal power into 100Ω load. A three
pin serial interface is used to program an 8-bit internal register
to set each port’s supply current with 0.5mA step size. This
flexibility allows the DSP to optimize each port separately
during modem training.
The device is supplied in a thermally-enhanced small footprint
(4mmx4mm) 24 lead QFN package. The ISL1561 is specified
for operation over the full -40°C to +85°C industrial
temperature range and is Pb-free RoHS compliant.
Features
• Internal fixed gain of 11.6V/V to transformer (see Figure 3)
• 360mA output drive capability
• 41.8VP-P differential output drive into 100Ω in class G mode
• VDSL2 8b profile MTPR of -64dBc
• VDSL2 17a profile MTPR of -60dBc
• ADSL2+, VDSL2 8b and 17a power consumption of 520mW,
610mW and 411mW respectively
• 8-bit programmable register to set supply current on each
port
• 3 pin serial port interface
Applications
• Dual port ADSL2+ and VDSL2 DSLAM
Alternate Part
• ISL1591 Class AB VDSL Driver
+14V
SCLK
SDATA
CS
SERIAL
INTERFACE
BIAS
CURRENT
SETTING
POWER MANAGEMENT
BOOST
AFE
INP
SWITCH SIGNAL
BOTH PORTS
SUPPLY
RAILS OF
LINE DRIVERS
ANALOG
INPUT
CLASS
AB
DRIVER
1 OF 2
PORTS
OUTPUT OF
DRIVER
FIGURE 1. BLOCK DIAGRAM
CPP
CPSW
CMM
CMSW
OUT
900
800 8b CLASS AB
700
600 17a CLASS AB
500
400
300 8b CLASS G
200
100 17a CLASS G
0
2 4 6 8 10 12 14 16 18 20
Tx POWER (dBm)
FIGURE 2. CLASS G+ vs CLASS AB DRIVER TOTAL POWER
February 26, 2013
FN7941.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas LLC 2012, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL1561
Electrical Specifications VSP = +14V, RL-DIFF = 51Ω differential (emulating transformer input load), Refer to Figure 3, TA = +25°C. Ports
tested separately unless otherwise indicated.(Continued)
PARAMETER
DESCRIPTION
CONDITIONS
MIN MAX
(Note 6) TYP (Note 6) UNIT
ILOW
Input Low Current for Pull-up Pins CS, VIN = 0V
BOOST
-88 -73 -58
µA
ILOW
Input Low Current for Pull-down Pins
SCLK, SDATA
VIN = 0V
-0.2 0 +0.2 µA
SUPPLY CHARACTERISTICS
VS
VCPP
VCPSW
VCMM
VCMSW
ISP
Operating Supply Voltage
Voltage on the CPP Pin
Maximum Voltage on the CPSW Pin
Voltage on the CMM Pin
Minimum Voltage on the CMSW Pin
Positive Supply Current per Port
+10 +14 +14.7
BOOST = 0V (Class AB)
7
BOOST = 0V (Class AB)
14
BOOST = 0V (Class AB)
7
BOOST = 0V (Class AB)
0
All outputs at 0V, BOOST = 0V, SDATA = 8’h7F
for Registers 3 and 7
17.5 19.5 21.5
V
V
V
V
V
mA
All outputs at 0V, BOOST = 0V, SDATA = 8’h1C
for Registers 3 and 7
9.8 10.3 10.8
mA
All outputs at 0V, BOOST = 0V, SDATA = 8’h0F 6.8 7.2 7.6
for Registers 3 and 7
mA
ISP (Power-down) Supply Current per Port
All outputs at 0V, BOOST = 0V, SDATA = 8’h80 2.0 2.5 3.0
for Registers 3 and 7
mA
OUTPUT CHARACTERISTICS
VOUT
Loaded Output Swing High
(Single-ended to GND)
RL = 51Ω, Class AB (see Figure 3)
11.9 12.4
V
Loaded Output Swing High
(Single-ended to GND)
RL = 51Ω, Class AB (see Figure 3)
1.6 2.1
V
IOL
Linear Output Current
RL = 10Ω, f = 100kHz, THD = -60dBc (5Ω
±360
mA
differential)
VOS-DM
Differential Output Offset Voltage
VOS-CM
Common Mode Output Offset Voltage
INPUT CHARACTERISTICS
SDATA = 8’h1C
SDATA = 8’h1C (Offset from input VCM)
-125 18 +125 mV
6.85
7.09 mV
CMIR
Common Mode Input Range at each of Class AB
the 4 Non-inverting Input Pins
+4.5
+9.5
V
CMRR
PSRR
DC Common Mode Rejections for each
Port. VCM = +4.5V to +9.5V
DC Power Supply Rejections for each
Port to Differential Output (Input
Referred)
VCM to Differential Mode Output (Input
Referred) ISP = 10mA/port
VCM to Common Mode Output (Output
Referred) ISP = 10mA/port
+VS = +7V to +14V, GND = 0V, ISP = 10mA/port
66
40
74
dB
dB
dB
DC Power Supply Rejections for each
Port to Common Mode Output (Output
Referred)
+VS = +7V to +14V, GND = 0V, ISP = 10mA/port
55
dB
RIN Input Resistance
Differential
5.0 6.0 7.1
kΩ
DIGITAL
fCLK Clock Frequency
0.1 10 MHz
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
5 FN7941.1
February 26, 2013
5 Page 
ISL1561
PARAMETER
t
tr/tf
tHC
tSD
tHC
tSC
tW
TABLE 1. SERIAL TIMING DIAGRAM
RECOMMENDED OPERATING RANGE
≥100ns
0.05*t
≥7ns
≥10ns
≥2.8ns
≥0.5ns
0.50*t
DESCRIPTION
Clock Period
Clock Rise/Clock Fall
Data Hold Time
Data Setup Time
CS Hold Time
CS Setup Time
Clock Pulse Width
Boost Control
Table 2 summarizes the logic of register MSB on boost operations followed by Figure 29 with the recommended look ahead timing for
the boost signal.
Reg3 8’h[7]
0
X
1
X
NOTE: X = do not care
TABLE 2. REGISTER MSB ON BOOST OPERATION
Reg7 8’h[7]
BOOST PIN
X1
01
1X
X0
BOOST OPERATION
1
1
0
0
SIGNAL
PARAMETER
td
td
BOOST
FIGURE 29. SERIAL TIMING DIAGRAM
TABLE 3. EXTERNAL BOOST SIGNAL TIMING PARAMETERS
RECOMMENDED OPERATING RANGE
100ns
DESCRIPTION
Look ahead boost
11 FN7941.1
February 26, 2013
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ISL1561.PDF ] | |
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