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PDF 74HC2G126DC Data sheet ( Hoja de datos )

Número de pieza 74HC2G126DC
Descripción Dual buffer/line driver
Fabricantes NXP Semiconductors 
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No Preview Available ! 74HC2G126DC Hoja de datos, Descripción, Manual

74HC2G126; 74HCT2G126
Dual buffer/line driver; 3-state
Rev. 5 — 18 December 2013
Product data sheet
1. General description
The 74HC2G126; 74HCT2G126 is a dual buffer/line driver with 3-state outputs controlled
by the output enable inputs (nOE). Inputs include clamp diodes. This enables the use of
current limiting resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
Wide operating voltage from 2.0 V to 6.0 V
Input levels:
For 74HC2G126: CMOS level
For 74HCT2G126: TTL level
Complies with JEDEC standard no. 7A
Symmetrical output impedance
High noise immunity
Low power dissipation
Balanced propagation delays
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74HC2G126DP 40 C to +125 C TSSOP8
74HCT2G126DP
74HC2G126DC 40 C to +125 C VSSOP8
74HCT2G126DC
74HC2G126GD 40 C to +125 C XSON8
74HCT2G126GD
Description
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
Version
SOT505-2
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; body 3 2 0.5 mm

1 page




74HC2G126DC pdf
NXP Semiconductors
74HC2G126; 74HCT2G126
Dual buffer/line driver; 3-state
Table 7. Static characteristics …continued
Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb = 25 C.
Symbol Parameter
Conditions
Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit
Min Typ Max
Min
Max
ICC supply current VI = VCC or GND; IO = 0 A; - - 10
VCC = 6.0 V
CI input capacitance
- 1.0 -
CO output
capacitance
- 1.5 -
-
-
-
20 A
- pF
- pF
74HCT2G126
VIH HIGH-level input VCC = 4.5 V to 5.5 V
voltage
2.0 1.6
-
2.0
-V
VIL LOW-level input VCC = 4.5 V to 5.5 V
voltage
- 1.2 0.8
-
0.8 V
VOH HIGH-level
VI = VIH or VIL; VCC = 4.5 V
output voltage
IO = 20 A
4.4 4.5
-
4.4
IO = 6.0 mA
3.84 4.32
-
3.7
VOL LOW-level output VI = VIH or VIL; VCC = 4.5 V
voltage
IO = 20 A
- 0 0.1
-
IO = 6.0 mA
- 0.16 0.33
-
II
input leakage
VI = VCC or GND; VCC = 5.5 V
-
- 1.0
-
current
-V
-V
0.1 V
0.4 V
1.0 A
IOZ
ICC
ICC
CI
CO
OFF-state output VI = VIH or VIL; VO =
current
VCC or GND; VCC = 5.5 V
supply current
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
additional supply per input; VCC = 4.5 V to 5.5 V;
current
VI = VCC 2.1 V; IO = 0 A
input capacitance
output
capacitance
-
-
-
-
-
- 5.0
- 10
- 375
1.0 -
1.5 -
-
-
-
-
-
10
20 A
410 A
- pF
- pF
11. Dynamic characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 8.
Symbol Parameter Conditions
Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit
Min Typ[1] Max
Min
Max
74HC2G126
tpd propagation nA to nY; see Figure 6
delay
VCC = 2.0 V
[2]
-
35 115
-
135 ns
VCC = 4.5 V
- 11 23
-
27 ns
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
- 10 -
- 8 20
-
-
- ns
23 ns
74HC_HCT2G126
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 18 December 2013
© NXP B.V. 2013. All rights reserved.
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5 Page





74HC2G126DC arduino
NXP Semiconductors
74HC2G126; 74HCT2G126
Dual buffer/line driver; 3-state
XSON8: plastic extremely thin small outline package; no leads;
8 terminals; body 3 x 2 x 0.5 mm
SOT996-2
D BA
terminal 1
index area
L1
L2
e1
eb
14
E A A1
detail X
v CAB
wC
y1 C
C
y
L
8
5
0 1 2 mm
scale
X
Dimensions (mm are the original dimensions)
Unit(1)
A A1 b D E e e1 L L1 L2 v w y y1
max 0.05 0.35 2.1 3.1
0.5 0.15 0.6
mm nom 0.5
0.5 1.5
0.1 0.05 0.05 0.1
min 0.00 0.15 1.9 2.9
0.3 0.05 0.4
Outline
version
References
IEC
JEDEC
JEITA
SOT996-2
Fig 11. Package outline SOT996-2 (XSON8)
74HC_HCT2G126
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 18 December 2013
European
projection
sot996-2_po
Issue date
07-12-21
12-11-20
© NXP B.V. 2013. All rights reserved.
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