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PDF FAH4840 Data sheet ( Hoja de datos )
| Número de pieza | FAH4840 | |
| Descripción | Haptic Driver | |
| Fabricantes | Fairchild Semiconductor | |
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October 2013
FAH4840
Haptic Driver for Linear Resonant Actuators (LRAs)
Features
Direct Drive of LRA (Linear Resonant Actuator)
External PWM Input (10 kHz to 250 kHz)
with Divider
Internal Motor Enable / Disable Input
Auto Resonant Tracking
LDO Provides Stable Haptic Effect with
Battery Depletion
Low Shutdown Current: < 5 nA
Fast Wake-Up Time
Nearly Rail-to-Rail Output Swing
Thermal Shutdown, Over-Current Shutdown
Register-Based Control by I2C
Immersion TouchSense® 3000 Certified
Package: 8- Lead MicroPak™ MLP
All trademarks are the property of their respective owners.
Description
The FAH4840 is a high-performance amplifier for
mobile phones and other hand-held devices. The
haptic driver takes a single-ended PWM input signal to
control a Linear Resonant Actuator (LRA). The device
utilizes an external 10 kHz to 250 kHz PWM signal
capable of meeting the wide range of resonant
frequencies needed for an LRA haptics applications.
The FAH4840 register map is accessible through an
I2C serial communication port.
Applications
Mobile Phones
Handheld Devices
Any Key pad interface
Ordering Information
Part Number Top Mark Operating Temperature Range Package Packing Method Quantity
FAH4840L8X
YB
-40°C to +85°C
MicroPak™ MLP
Reel
5000
© 2013 Fairchild Semiconductor Corporation
FAH4840 • Rev. 1.0.0
www.fairchildsemi.com
Free Datasheet http://www.datasheet4u.com/
1 page  
AC Electrical Characteristics
TA = 25°C, VDD = 3.3 V, VREG=2.0 V, unless otherwise noted.
Symbol
Parameter
Conditions
tWU Wake-Up Time
PWM=80/20% Duty Cycle, HEN/PWM LOW
to HIGH, Measurement Point PWM = 50%,
Output Point = 90%
tSD
Restrk
Shutdown Time
Auto Resonance Tracking
PWM=80/20% Duty Cycle, HEN HIGH to
LOW, Measurement Point HEN = 50%,
Output Point = 90%
PWM=22.4 kHz 80/20% Duty, RL= 25 Ω
Min. Typ. Max. Unit
1 150 µs
0.2 150.0 µs
-2.5 2.5 Hz
tWU
Figure 4.
Haptic Enable / Disable Functional Timing
tSD
Table 1.
VDD vs. VREG Supply Values
VREG_OUT
(Programmed Voltage)
2.5
1.4
1.6
1.8
2.0
2.2
2.4
VDD (V)
2.7
1.4
1.6
1.8
2.0
2.2
2.4
2.6
3.0
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.3
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
© 2013 Fairchild Semiconductor Corporation
FAH4840 • Rev. 1.0.0
5
www.fairchildsemi.com
Free Datasheet http://www.datasheet4u.com/
5 Page 
Table 5.
Address:
Reset Value:
STATUS1
0x02
xxxx111x
Bit #
Name
Type
Function
7:4 Reserved
3 VDD_G
0: Input voltage is not good (less UVLO), Input voltage is less than 2.3 V
R (rising), 2.1 V (falling)
1: Input voltage is good (over UVLO)
2
VREG_OUT_
G
0: Regulator output is not good (VREG_OUT is less than 70% of VREG_OUT
R programmed)
1: Regulator output is good(3)
1 VOT
0: Over temperature protection is tripped
R 1: Over temperature protection is not tripped
0 Reserved
Note:
3. HEN must be HIGH for VREG_OUT to be enabled.
Table 6.
Address:
Reset Value:
CTRL_DIV1
0x03
01010011
Bit #
7:0
Name
PWM_DIV[7:0]
Type
R/W
Function
LSB of the PWM divisor. For example, if the intended resonance frequency is
175 Hz and the PWM input clock frequency is 40 kHz, program the
PWM[15:0] register as:
PWM_DIV[15:0] = (1/175)/(1/40 kHz) = 228(decimal) = E4(HEX)
PWM_DIV[15:8] = 00
PWM_DIV[7:0] = E4
Counter range is from 01 to E4.
Default is 83
Table 7.
Address:
Reset Value:
CTRL_DIV2
0x04
00000000
Bit #
7:0
Name
PWM_DIV[15:8]
Type
R/W
MSB of the PWM divisor.
Default is 0
Function
© 2013 Fairchild Semiconductor Corporation
FAH4840 • Rev. 1.0.0
11
www.fairchildsemi.com
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet FAH4840.PDF ] | |
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