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Mitsubishi Electric Semiconductor |
MITSUBISHI SEMICONDUCTOR <TRANSISTOR ARRAY>
M81049P/SP/FP
OCTAL D-TYPE FLIP-FLOP DRIVER WITH CLEAR
DESCRIPTION
M81049 is octal D-type flip-flop driver by 20-pin package. It
has 8 same circuit units which is composed of D-type flip-flop
logic circuit and high voltage NchMOS output transistor.
M81049 has a common direct clear input and a common
clock input.
FEATURES
● Lineup with three packages
● High breakdown voltage (BVDSX ≥ 40V)
● Drain output current (IDS(max) = 200mA)
● With input protection diodes
● Pin assignment of input-output flow through
● Wide operating temperature range (Ta = –40 to +85°C)
APPLICATION
LED drive
PIN CONFIGURATION (TOP VIEW)
INPUT
CLR 1
D1 2
D2 3
D3 4
D4 5
D5 6
D6 7
D7 8
D8 9
CLK 10
20 VDD
19 Y1
18 Y2
17 Y3
16 Y4
OUTPUT
15 Y5
14 Y6
13 Y7
12 Y8
11 GND
Package type 20P4(P)
20P4B(SP)
20P2N(FP)
FUNCTION
The common direct clear input and common clock input are
connected to every circuit unit by the same way. Signal at the
D inputs is transferred to Y outputs by D-type flip-flops on the
positive-going edge of the clock pulse.
If CLR is set to “L”, outputs Y1-Y8 will be altogether set to “H”
regardless of D1-D8 and CLK.
The maximum drain current of an output is 200mA. The
maximum between drain-source is 40V.
www.DataSheet.net/
LOGIC DIAGRAM (POSITIVE LOGIC)
CLK 10
CLR 1
Y1
19
DQ
CK
R
Y2
18
DQ
CK
R
Y3
17
DQ
CK
R
Y4
16
DQ
CK
R
Y5
15
DQ
CK
R
Y6
14
DQ
CK
R
Y7
13
DQ
CK
R
Y8
12
20 VDD
DQ
CK
R
23456789
D1 D2 D3 D4 D5 D6 D7 D8
11 GND
Jun. 2009
Datasheet pdf - http://www.DataSheet4U.co.kr/
FUNCTION TABLE (EACH CHANNEL)
CLR
L
H
H
H
H
INPUT
CLK
X
↑
↑
L
↓
D
X
L
H
X
X
OUTPUT : Y
H
H
L
Latched
Latched
↑ : “L” to “H”
↓ : “H” to “L”
H : High level
L : Low level
X : Irrelevant
MITSUBISHI SEMICONDUCTOR <TRANSISTOR ARRAY>
M81049P/SP/FP
OCTAL D-TYPE FLIP-FLOP DRIVER WITH CLEAR
TIMING DIAGRAM
CLK
D
CLR
Y
5V
GND
5V
GND
5V
GND
VOH
VOL
ABSOLUTE MAXIMUM RATINGS (Unless otherwise noted, Ta = –40 ~ +85°C)
Symbol
VDD
VDS
VI
IDS
Parameter
Supply voltage
Drain-to-source voltage
Input voltage
Drain output current
Conditions
Output, H
Current per circuit output, L
Pd Power dissipation
Ta = 25°C,
when mounted on board
Topr Operating temperature
Tstg Storage temperature
www.DataSheet.net/
M81049P
M81049SP
M81049FP
Ratings
7
–0.5 ~ +40
–0.5 ~ VDD
200
1.79
1.47
1.10
–40 ~ +85
–55 ~ +125
Unit
V
V
V
mA
W
°C
°C
RECOMMENDED OPERATING CONDITIONS (Unless otherwise noted, Ta = –40 ~ +85°C)
Symbol
Parameter
VDD Supply voltage
VDS Drain-to-source voltage
VIH “H” input voltage
VIL “L” input voltage
P
Drain output current (Current per
IDS 1 circuit when 8 circuits are com- SP
ing on simultaneously)
FP
VIN Input voltage
tr,t f Rise time, Fall time, drain output
tsu Setup time before CLK ↑
th Hold time, data after CLK ↑
tw Pulse duration
f Clock frequency
Conditions
Duty Cycle no more than 48%
Duty Cycle no more than 100%
Duty Cycle no more than 40%
Duty Cycle no more than 100%
Duty Cycle no more than 33%
Duty Cycle no more than 100%
VDD = 4.5V
VDD = 4.5V
VDD = 4.5V
VDD = 4.5V
VDD = 4.5V
min
4.5
0
0.7VDD
0
0
0
0
0
0
0
0
0
20
5
40
—
Limits
typ
5.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
max
5.5
40
VDD
0.3VDD
200
140
200
125
200
115
VDD
500
—
—
—
20
Unit
V
V
V
V
mA
V
ns
ns
ns
ns
MHz
Jun. 2009
2
Datasheet pdf - http://www.DataSheet4U.co.kr/
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