NB4N111K 반도체 회로 부품 판매점
3.3V Differential In 1:10 Differential Fanout Clock Driver
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 ON Semiconductor |
NB4N111K
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3.3V Differential In 1:10
Differential Fanout Clock
Driver with HCSL Level
Output
Description
The NB4N111K is a differential input clock 1 to 10 HCSL fanout
buffer, optimized for ultra low propagation delay variation. The
NB4N111K is designed with HCSL clock distribution for FBDIMM
applications in mind.
Inputs can accept differential LVPECL, CML, or LVDS levels.
Single−ended LVPECL, CML, LVCMOS or LVTTL levels are
accepted with the proper VREFAC supply (see Figures 5, 10, 11, 12,
and 13). Clock input pins incorporate an internal 50 W on die
termination resistors. Outputs can interface with LVDS with proper
termination (See Figure 15).
The NB4N111K specifically guarantees low output–to–output
skews. Optimal design, layout, and processing minimize skew within
a device and from device to device. System designers can take
advantage of the NB4N111K’s performance to distribute low skew
clocks across the backplane or the motherboard.
Features
• Typical Input Clock Frequencies: 100, 133, 166, 200, 266, 333, and
400 MHz
• 340 ps Typical Rise and Fall Times
• 800 ps Typical Propagation Delay
• Dtpd 100 ps Maximum Propagation Delay Variation Per Each
Differential Pair
• <1 ps RMS Additive Clock jitter
• Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
• Differential HCSL Output Level or LVDS with Proper Termination
• These are Pb−Free Devices
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1 32
QFN32
MN SUFFIX
CASE 488AM
MARKING DIAGRAM*
32
1
NB4N
111K
AWLYYWWG
A = Assembly Site
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
VTCLK
CLK
CLK
VTCLK
VCC
GND
Q0
Q0
Q1
Q1
RREF
Q8
Q8
Q9
IREF Q9
Figure 1. Pin Configuration (Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2010
June, 2010 − Rev. 4
1
Publication Order Number:
NB4N111K/D
IREF 1
VTCLK 2
CLK 3
CLK 4
VTCLK 5
Q9 6
Q9 7
GND 8
NB4N111K
NB4N111K
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Exposed Pad (EP)
24 VCC
23 Q3
22 Q3
21 Q4
20 Q4
19 Q5
18 Q5
17 VCC
Figure 2. Pinout Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1
IREF
Output
Output current programming pin. Connect to GND. (See Figure 9).
2, 5
VTCLK,
− Internal 50 W Termination Resistor connection Pins. In the differential configuration
VTCLK
when the input termination pins are connected to the common termination voltage,
and if no signal is applied then the device may be susceptible to self−oscillation.
3 CLK LVPECL Input CLOCK Input (TRUE)
4 CLK LVPECL Input CLOCK Input (INVERT)
8
GND
− Supply Ground. GND pin must be externally connected to power supply to
guarantee proper operation.
9, 16, 17, 24, 25, 32
VCC
− Positive Supply pins. VCC pins must be externally connected to a power supply to
guarantee proper operation.
6, 10, 12, 14, 18, 20, Q[09−0]
22, 26, 28, 30
HCSL or
Noninverted Clock Output. (For LVDS levels see Figure 15)
LVDS Output
7, 11, 13, 15, 19, 21,
23, 27, 29, 31
Q[09−0]
HCSL or Inverted Clock Output. (For LVDS levels see Figure 15)
LVDS Output
Exposed Pad
EP
GND
Exposed Pad. The thermally exposed pad (EP) on package bottom (see case
drawing) must be attached to a sufficient heat−sinking conduit for proper thermal
operation. (Note 1)
1. The exposed pad must be connected to the circuit board ground.
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NB4N111K driver
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상호 : 아이지 인터내셔날
전화번호 : 051-319-2877
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