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PDF PI2EQX5804 Data sheet ( Hoja de datos )
| Número de pieza | PI2EQX5804 | |
| Descripción | 5.0Gbps 4-lane PCIe Gen2 Redriver | |
| Fabricantes | Peregrine Semiconductor | |
| Logotipo |  |
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PI2EQX5804
5.0Gbps 4-Lane PCI Express Gen2 Re-Driver
with Equalization & Emphasis
Features
• Up to 5.0Gbps PCI Express Gen-2 Serial Re-driver
• Supporting 8 differential channels or 4 lanes of PCIe Interface
• Pin strapped and I2C configuration controls (3.3V Tolerant)
• Adjustable receiver equalization
• Adjustable transmitter amplitude and de-emphasis
• Variable input an output termination
• 1:2 channel broadcast
• Channel loop-back
• Electrical Idle fully supported
• Receiver detect and individual output control
• Single supply voltage, 1.2V ± 0.05V
• Power down modes
• Packaging: 100-contact LFBGA, Pb-free & Green
Description
Pericom Semiconductor’s PI2EQX5804 is a low power,
PCI-express compliant signal re-driver. The device provides
programmable equalization, amplification, and de-emphasis by
using 8 select bits, to optimize performance over a variety of
physical mediums by reducing Inter-symbol interference.
PI2EQX5804 supports eight 100-Ohm Differential CML data
I/O’s between the Protocol ASIC to a switch fabric, across
a backplane, or extends the signals across other distant data
pathways on the user’s platform.
The integrated equalization circuitry provides flexibility with
signal integrity of the PCI-express signal before the re-driver,
whereas the integrated de-emphasis circuitry provides flexibility
with signal integrity of the signal after the re-driver.
In addition to providing signal re-conditioning, Pericom’s
PI2EQX5804 also provides power management Stand-by mode
operated by a Power Down pin.
Block Diagram
xyRx+
xyRx-
xyTx+
xyTx-
+
−
+
− Equalizer
Input level detect
to control logic
Output
Controls
+
−
xyTx+
xyTx-
+
−
Output
Controls
A
B
Input level detect
to control logic
Equalizer
+
−
+
−
Data Lane Repeats 4 Times
xyRx+
xyRx-
SELy_x
Sy_x
Dy_x
DE_x
PD#
SDA
SCL
Control registers
& logic
Power
Management
I2C Control
Mode
LB#
RXD_x
RES_x
Ax
Pin Configuration (Top-Side View)
12
34
56 7 8
9 10
A VDD B0TX- B0TX+ VDD SCL SDA VDD B0RX+ B0RX- VDD
B A1RX+ GND GND A0RX - DE_A VDD A0TX- GND GND A1TX+
C A1RX- GND GND A0RX+ NC PD# A0TX+ GND GND A1TX-
D VDD B1TX+ B1TX- VDD D2_A NC VDD B1RX- B1RX+ VDD
E SEL0_A SEL1_A SEL2_A D0_A D1_A S0_A RXD_A S1_A SIG_A RX50_A
F RX50_B SIG_B S1_B RXD_B S0_B A1 SEL2_B LB# SEL1_B SEL0_B
G VDD A2RX- A2RX+ VDD MODE D0_B VDD A2TX+ A2TX - VDD
H B2TX+ GND GND B3TX- DE_B A0 B3RX- GND GND B2RX+
J B2TX- GND GND B3TX+ RESET# D1_B B3RX+ GND GND B2RX-
K VDD A3RX+ A3RX- VDD D2_B A4
VDD A3TX- A3TX+ VDD
08-0218
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PS8926B
09/04/08
1 page  
www.DataSheet4U.com
PI2EQX5804
5.0Gbps 4-Lane PCI Express Gen2 Re-Driver with
Equalization & Emphasis
Equalizer Configuration
The PI2EQX5804 input equalizer compensates for signal attenuation and Inter-Symbol Interference (ISI) re-
sulting from long signal traces or cables, vias, signal crosstalk and other factors, by boosting the gain of high-
frequency signal components. Because either too little, or too much, signal compensation may be non-optimal
eight levels are provided to adjust for any application.
Equalizer configuration is performed in two ways determined by the state of the MODE pin. When the device
first powers up, the SELx_[A:B] input pins are read into the appropriate control registers to set the equalization
characteristic. If the MODE pin is low, reprogramming of these control registers via I2C is allowed.
Each group of four channels, A and B, has separate equalization control, and all four channels within the group
are assigned the same configuration state. The Equalizer Selection table below describes pin strapping options
and associated operation of the equalizer. Refer to the section on I2C programming for information on soft-
ware configuration of the equalizer.
Equalizer Selection
SEL2_[A:B]
0
0
0
0
1
1
1
1
SEL1_[A:B]
0
0
1
1
0
0
1
1
SEL0_[A:B]
0
1
0
1
0
1
0
1
@1.25GHz
0.5dB
0.6dB
1.0dB
1.9dB
2.8dB
3.6dB
5.0dB
7.7dB
@2.5GHz
1.2dB
1.5dB
2.6dB
4.3dB
5.8dB
7.1dB
9.0dB
12.3dB
Output Configuration
The PI2EQX5804 provides flexible output strength and emphasis controls to provide the optimum signal to
pre-compensate for losses across long trace or noisy environments so that the receiver gets a clean eye open-
ing. Control of output configuration is grouped for the A and B channels, so that each channel within the
group has the same setting.
Output configuration is performed in two ways depending on the state of the MODE pin. When the device
first powers up, the Sx_[A:B], and Dx_[A:B] input pins are read into the appropriate control registers to set the
power-on state. If the MODE pin is low, reprogramming of these control registers via I2C is allowed.
The Output Swing Control table shows available configuration settings for output level control, as specified
using the Sx_y pins and registers.
08-0218
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PS8926B
09/04/08
5 Page 
www.DataSheet4U.com
Register Description
PI2EQX5804
5.0Gbps 4-Lane PCI Express Gen2 Re-Driver with
Equalization & Emphasis
Byte 0 - Signal Detect (SIG)
SIG_xy=0=low input signal, SIG_xy=1=valid input signal
Bit 7
6
5
4
3
2
Name
SIG_A0 SIG_B0 SIG_A1
SIG_B1
SIG_A2 SIG_B2
Type
R
R
R
R
RR
Power-on
X
X
X
X
X
X
State
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
1
SIG_A3
R
X
0
SIG_B3
R
X
The Signal Detect register provides information on the instantaneous status of the channel input from the Input Level
Threshold Detect circuit. If the input level falls below the Vth- level the relevant SIG_xy bit will be 0, indicating a low-
level noise or electrical idle input, resulting in the outputs going to the high-impedance off state or squelch mode. If the
input level is above Vth-, then SIG_xy is 1, indicating a valid input signal, and active signal recovery operation.
Byte 1 - Receiver Detect Output Register (RX50)
LB_xyxy#=0=loopback mode, LB_xyxy#=1=normal mode, DE_x=0=pre-emphasis, DE_x=1=de-emphasis
Bit 7
6
5
4
3
2
Name RX50_A0 RX50_B0 RX50_A1 RX50_B1 RX50_A2 RX50_B2
Type
R
R
R
R
RR
Power-on
X
X
X
X
X
X
State
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
1
RX50_A3
R
X
0
RX50_B3
R
X
The RX50_xy bits report the result of a receiver detection cycle. One bit is assigned for each channel of the device.
RX50_xy is at a logic 1 level indicating a load and receiver was detected. When RX50_xy is 0 then a load device was
not detected. The RX50 register is read-only, and is undefined after power-up until a Receiver Detection cycle com-
pletes.
Byte 2 - Loopback and Emphasis Control Register (LBEC)
LB_xyxy#=0=loopback mode, LB_xyxy#=1=normal mode, DE_x=0=pre-emphasis, DE_x=1=de-emphasis
Bit 7
6
5
43
2
10
Name LB_A0B0# LB_A1B1# LB_A2B2# LB_A3B3# DE_A DE_B rsvd rsvd
Type
R/W
R/W
R/W
R/W
R/W R/W
R
R
Power-on
LB#
LB#
LB#
State
LB#
DE_A DE_B
X
X
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
Individual control for each lane is provided for the loopback function via this register.
08-0218
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PS8926B
09/04/08
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet PI2EQX5804.PDF ] | |
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