|
|
PDF PI2EQX5864 Data sheet ( Hoja de datos )
| Número de pieza | PI2EQX5864 | |
| Descripción | 5.0Gbps 4-Lane PCI Express GenII Re-Driver | |
| Fabricantes | Pericom Semiconductor Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de PI2EQX5864 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
PI2EQX5864
5.0Gbps 4-Lane PCI Express GenII Re-Driver
with Equalization, Emphasis, &I2C Control
Features
• Up to 5.0Gbps PCI Express Gen-2 Serial Re-driver
• Supporting 8 differential channels or 4 lanes of PCIe Interface
• I2C configuration controls (3.3V Tolerant)
• Adjustable receiver equalization and transmitter de-emphasis
and output levels
• Variable input an output termination
• 1:2 channel broadcast
• Channel loop-back
• Electrical Idle fully supported
• Receiver detect and individual output control
• Single supply voltage, 1.2V ± 0.05V
• Power down modes
• Packaging: 56-contact TQFN, Pb-free & Green
Description
Pericom Semiconductor’s PI2EQX5864 is a low power,
PCI-express compliant signal re-driver. The device provides
programmable equalization, amplification, and de-emphasis by
using 8 select bits, to optimize performance over a variety of
physical mediums by reducing Inter-symbol interference.
PI2EQX5864 supports eight 100-Ohm Differential CML data
I/O’s between the Protocol ASIC to a switch fabric, across
a backplane, or extends the signals across other distant data
pathways on the user’s platform.
The integrated equalization circuitry provides flexibility with
signal integrity of the PCI-express signal before the re-driver,
whereas the integrated de-emphasis circuitry provides flexibility
with signal integrity of the signal after the re-driver.
In addition to providing signal re-conditioning, Pericom’s
PI2EQX5864 also provides power management Stand-by mode
operated by a Bus Enable pin.
Block Diagram
xyRx+
xyRx-
xyTx+
xyTx-
+
−
+
Input level detect
to control logic
−
Equalizer
Output
Controls
+
−
xxTx+
xxTx-
+
−
Output
Controls
A
B
Input level detect
to control logic
Equalizer
+
−
+
−
Data Lane Repeats 4 Times
xyRx+
xyRx-
Control registers
& logic
Mode
LB#
RXD_x
RES_x
Power
Management
SDA
SCL
I2C Control
Ax
Pin Configuration
VDD
A0RX+
A0RX-
B0TX+
B0TX-
VDD
A1RX+
A1RX-
B1TX+
B1TX-
VDD
A2RX+
A2RX-
B2TX+
B2TX-
VDD
A3RX+
A3RX-
B3TX+
B3TX-
56 55 54 53 52 51 50 49
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 22 23 24 25 26 27 28
A0TX+
A0TX-
B0RX+
B0RX-
VDD
A1TX+
A1TX-
B1RX+
B1RX-
VDD
A2TX+
A2TX-
B2RX+
B2RX-
VDD
A3TX+
A3TX-
B3RX+
B3RX-
VDD
07-0277
1
PS8934A
01/21/08
1 page  
www.DataSheet4U.com
PI2EQX5864
5.0Gbps 4-Lane PCI Express GenII Re-Driver
with Equalization, Emphasis and I2C Control
Receiver Detect
Automatic Receiver Detection is a feature that can set the number of active channels. By sensing the presence of a load device
on the output, the channel can be automatically enabled for operation. This allows the PI2EQX5864 to configure itself properly
depending on the devices it is communicating with, whether it is a 4-lane, 3-lane, 2-lane or just 1-lane device or adapter card.
Receiver Detect is enabled by the RXD_A, or RXD_B pins, or alternatively via I2C programming. When RXD_A or RXD_B is set
to low, the Receiver Detect operation for that group of channels is disabled, and those channels go directly to 50-Ohm input termi-
nation to ground and 50-Ohm output termination to Vdd (for a valid differential channel input level) or to 2K-Ohm (if the signal
level is less than the threshold level).
The RES_A#, and RES_B# inputs are used to reset the receiver detect state machine to its initial state. RES_A# and RES_B#
control the received detect reset for the A and B group of channels respectively. The start of the receiver detect cycle starts when
RES_A# or RES_B# transitions from low to high.
When a Receiver Detect cycle begins the differential channel pins are enabled with a 2K-Ohm pullup to Vdd. A 50-Ohm Receiver
termination will change the pin level. This pin level is evaluated after a fixed time-out, and the channel is then set into the proper
operating state. The register bits RX50_Ax and RX50_Bx represent the receiver detect result for their specific channels.
The I/O operation table summarizes the relationships and operation of receiver detect and other signals involved with I/O control.
I/O Operation Control
Control Inputs
PD# PRSNT2# RXD_x RES_x#
0X
XX
11
XX
10
00
10
01
10
01
10
10
10
11
10
11
10
11
Detection
States
RX50 SIG_x
XX
XX
XX
X0
X1
XX
0X
10
11
Data Channel I/O
Input Termination Output Termination
Hi-Z Hi-Z
Hi-Z Hi-Z
Hi-Z 2K-Ohm pull-up
50-Ohm pull-
down
50-Ohm pull-
down
Hi-Z
Hi-Z
2K-Ohm pull-up
50-Ohm pull-up
2K-Ohm pull-up
2K-Ohm pull-up
50-Ohm pull-
down
2K-Ohm pull-up
50-Ohm pull-
down
50-Ohm pull-up
Mode
Full IC power down, all chan-
nels disabled
No receiver (defined by
PRSNT2#), all channels
disabled
Channel disabled, output
pulls to Vdd. Receiver detect
reset
Channel enabled, no input
signal, output pulls to Vdd.
Receiver detect disabled
Channel enabled, valid input
signal detected, output driv-
ing. Receiver detect disabled.
Channel disabled. Receiver
detect reset.
Channel disabled, output
pulls to Vdd. Receiver detect
enabled, no receiver detected.
Channel inactive, output pulls
to Vdd. Receiver detect en-
abled, receiver detected. No
input signal
Channel active, valid input
signal detected, output driv-
ing. Receiver detect enabled,
load detected.
07-0277
5
PS8934A
01/21/08
5 Page 
www.DataSheet4U.com
I2C Data Transfer
1. Read sequence
PI2EQX5864
PI2EQX5864
ACK DATA OUT ACK
PI2EQX5864
5.0Gbps 4-Lane PCI Express GenII Re-Driver
with Equalization, Emphasis and I2C Control
ACK DATA OUT N NO ACK
I2C Master
DEV SEL R / W
2. Write sequence
PI2EQX5864
ACK
ACK
ACK
ACK
ACK
I2C Master
DEV SEL R / W DUMMY BYTE
DATA IN 1
3. Combined sequence
PI2EQX5864
ACK DUMMY BYTE ACK
ACK DATA OUT 1 ACK
DATA IN N
ACK DATA OUT N NO ACK
I2C Master
DEV SEL R / W
DEV SEL R / W
Notes:
1. only block read and block write from the lowest byte
are supported for this application.
2. for some I2C application, an offset address byte will be
presented at the second byte in write command, which
is called dummy byte here and will be simply ignored in
this application for correct interoperation.
07-0277
11
PS8934A
01/21/08
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet PI2EQX5864.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| PI2EQX5864 | 5.0Gbps 4-Lane PCI Express GenII Re-Driver | Pericom Semiconductor Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |