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IR2111S 반도체 회로 부품 판매점

HALF-BRIDGE DRIVER



International Rectifier 로고
International Rectifier
IR2111S 데이터시트, 핀배열, 회로
www.DataSheet4U.com
Data Sheet No. PD60028-M
IR2111(S) & (PbF)
Features
Floating channel designed for bootstrap operation
Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune
Gate drive supply range from 10 to 20V
Undervoltage lockout for both channels
CMOS Schmitt-triggered inputs with pull-down
Matched propagation delay for both channels
Internally set deadtime
High side output in phase with input
Also available LEAD-FREE
HALF-BRIDGE DRIVER
Product Summary
VOFFSET
600V max.
IO+/-
200 mA / 420 mA
VOUT
10 - 20V
ton/off (typ.)
750 & 150 ns
Deadtime (typ.)
650 ns
Description
Packages
The IR2111(S) is a high voltage, high speed power
MOSFET and IGBT driver with dependent high and
low side referenced output channels designed for half-
bridge applications. Proprietary HVIC and latch
immune CMOS technologies enable ruggedized
monolithic construction. Logic input is compatible with
standard CMOS outputs. The output drivers feature a
high pulse current buffer stage designed for minimum
driver cross-conduction. Internal deadtime is provided
8-Lead PDIP
to avoid shoot-through in the output half-bridge. The
floating channel can be used to drive an N-channel
power MOSFET or IGBT in the high side configuration which operates up to 600 volts.
8-Lead SOIC
Typical Connection
up to 600V
VCC
VCC
VB
IN IN HO
COM
LO
VS
TO
LOAD
(Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical connections
only. Please refer to our Application Notes and DesignTips for proper circuit board layout.
www.irf.com
1


IR2111S 데이터시트, 핀배열, 회로
www.DataSheet4U.com
IR2111(S) & (PbF)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions. Additional information is shown in figures 7 through 10.
Symbol
VB
VS
VHO
VCC
VLO
VIN
dVs/dt
PD
RthJA
TJ
TS
TL
Definition
High side floating supply voltage
High side floating supply offset voltage
High side floating output voltage
Low side and logic fixed supply voltage
Low side output voltage
Logic input voltage
Allowable offset supply voltage transient (figure 2)
Package power dissipation @ TA +25°C (8 Lead PDIP)
(8 lead SOIC)
Thermal resistance, junction to ambient
(8 lead PDIP)
(8 lead SOIC)
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
Min.
-0.3
VB - 25
VS - 0.3
-0.3
-0.3
-0.3
-55
Max.
625
VB + 0.3
VB + 0.3
25
VCC + 0.3
VCC + 0.3
50
1.0
0.625
125
200
150
150
300
Units
V
V/ns
W
°C/W
°C
Recommended Operating Conditions
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The VS offset rating is tested with all supplies biased at 15V differential.
Symbol
VB
VS
VHO
VCC
VLO
VIN
TA
Definition
High side floating supply absolute voltage
High side floating supply offset voltage
High side floating output voltage
Low side and logic fixed supply voltage
Low side output voltage
Logic input voltage
Ambient temperature
Min.
VS + 10
Note 1
VS
10
0
0
-40
Max.
VS + 20
600
VB
20
VCC
VCC
125
Units
V
°C
Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS. (Please refer to the Design Tip
DT97-3 for more details).
2 www.irf.com




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