PDF CS1087 Data sheet ( Hoja de datos )

Número de pieza	CS1087
Descripción	Vacuum Fluorescent Display Tube Driver
Fabricantes	ON Semiconductor
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No Preview Available ! www.DataSheet4U.com CS1087 Vacuum Fluorescent Display Tube Driver The VFD Driver is a microprocessor interface IC that drives a multiplexed VF (Vacuum Fluorescent) display tube. It consists of a 32–bit shift register, a 32–bit transparent data latch, a metal mask ROM, six 20 mA anode output drivers, twenty–three 2 mA anode output drivers, and three 50 mA grid drivers with output enables. Features • Power On Reset • Display Dimming Possible • Three, 50 mA Grid Drivers • Anode Options – DIP–40 and PCLL–44: – 6 @ 20 mA – 23 @ 2 mA • Anode Options – SO–28L: – 3 @ 20 mA – 15 @ 2 mA VIGN 12 V Regulator 5V GND VBAT VCC µP PORT PORT PORT GND PORT Chip Select Clock Data Out SPI Functions Anodes 1:29 0.1 µF VBB CS1087 FILAMENT VFD GRID1GRID2 GRID3 GND DOUT DIN GRID1 CLK GRID2 STB GRID3 GREN GND Figure 1. Application Diagram http://onsemi.com 40 1 DIP–40 WIDE BODY N SUFFIX CASE 711 PLCC–44 FN SUFFIX CASE 777 28 1 SO–28L DW SUFFIX CASE 751F ORDERING INFORMATION* Device CS1087XN40 Package DIP–40 WIDE BODY Shipping 9 Units/Rail CS1087XFN44 CS1087XFNR44 CS1087XDW28 CS1087XDWR28 PLCC–44 PLCC–44 SO–28L SO–28L 23 Units/Rail 500 Tape & Reel 27 Units/Rail 1000 Tape & Reel *For additional package options, consult your local ON Semiconductor sales office. DEVICE MARKING INFORMATION See general marking information in the device marking section on page 7 of this data sheet. © Semiconductor Components Industries, LLC, 2001 August, 2001 – Rev. 11 1 Publication Order Number: CS1087/D 1 page CS1087 GRID1 GRID2 GRID3 AN1 AN2 AN3 VBB GND POR VREG VREG AN23 AN24 AN25 AN26 AN27 AN28 AN29 GREN VREG STB VREG DIN VREG CLK VREG METAL MASK ROM DQ LE DQ LE DQ LE DQ LE DQ LE DQ LE DQ LE DQ LE DQ LE DQ LE DQ LE DQ LE DQ CLK R DQ CLK R DQ CLK R DQ CLK R DQ CLK R DQ CLK R DQ CLK R DQ CLK R DQ CLK R DQ CLK R DQ CLK R DQ CLK R DQ CLK R DQ LE VREG DQ CLK R DOUT Output Drive Capability Grid Outputs: 50 mA AN24–AN29: 20 mA AN1–AN23: 2.0 mA Figure 2. Block Diagram OPERATION DESCRIPTION Upon the initial application of power, the power on reset function will cause all of the anode and grid driver outputs to be off and all shift register outputs to be set low. Data is fed into the shift register through the DIN pin at the rising edge of the CLK input. Thirty two bits of data are capable of being stored by the shift register. Once the desired pattern is stored in the shift register, it can be transferred to the latch by setting the STB input high. The output of each latch drives its corresponding output stage. A logic high input to the shift register/latch will cause the corresponding output to turn on. A logic low input to the shift register/latch will cause the corresponding output to turn off. Please note that if the STB is held high, the outputs of the latch reflect the outputs of the corresponding shift register bits and will change if data is shifted in. The three GRID outputs are gated by the GREN input. When GREN is low, the GRID outputs are forced low regardless of the state of the corresponding latch output. When GREN is high, the GRID outputs correspond to the state of their respective latch outputs. The anode outputs, AN1 to AN29 are always enabled. The DOUT pin is the output of the last stage of the shift register to allow serial cascading of this IC with other devices. Data from the last stage of the shift register is supplied to the DOUT pin delayed by 1/2 CLK cycle. Data on the DOUT output changes with the falling edges of the CLK to prevent logic race conditions between the CLK and the DIN of the next IC in the serial chain. http://onsemi.com 5 5 Page Notes CS1087 http://onsemi.com 11 11 Page

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