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PDF IW4017B Data sheet ( Hoja de datos )
| Número de pieza | IW4017B | |
| Descripción | Decade Counter/Driver | |
| Fabricantes | IK Semiconductor | |
| Logotipo |  |
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TECHNICAL DATA
Counter/Divider
IW4017B
The IW4017B is 5-stage Johnson counter having 10 decoded outputs.
Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal.
Schmitt trigger action in the CLOCK input circuit provides pulse shaping
that allows unlimited clock input pulse rise and fall times.
The counter is advanced one count at the positive clock signal
transition if the CLOCK INHIBIT signal is low. Counter advancement via
the clock line is inhibited when the CLOCK INHIBIT signal is high. A
high RESET signal clears the counter to its zero count. Use of the Johnson
counter configuration permits high-speed operation, 2-input decode-gating
and spike-free decoded outputs. Anti-lock gating is provided, thus
assuring proper counting sequence. The decoded outputs are normally low
and go high only at their respective decoded time slot. Each decoded
output remains high for one full clock cycle. A CARRY-OUT signal
completes one cycle every 10 clock input cycles.
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package-temperature
range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
N SUFFIX
PLASTIC
16
1
16
1
DW SUFFIX
SOIC
ORDERING INFORMATION
IW4017BN Plastic
IW4017BD SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
www.datasheet4uPPII.NNc81o6==mGVNCDC
Clock
L
X
X
FUNCTION TABLE
Clock
Enable
X
H
X
L
Reset
L
L
H
L
Output State
no change
no change
reset counter
Q0=H, Q1-Q9=L,
C0=H
Advance to next
state
X L no change
X L no change
H L Advance to next
state
Carry Out=H for Q0,Q1,Q2,Q3 or Q4=H
Carry Out = L otherwise, X=don’t care
1
1 page  
IW4017B
CLOCK
CLOCK
INHIBIT
t su
50%
tf
50%
90% 90%
50% 50%
10% 10%
RESET
t PLH
t PHL
DECODE
Q1-Q9 OUTPUT
50%
t PHL
DECODE
Q0 OR
CARRY OUTPUT
90%
10%
50%
1/f max
50%
tr
50%
tw
50%
tw
50% 50%
50%
t PLH
10%
t
90%
50%
t rem
Figure 1. Switching Waveforms
Timing diagram
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet IW4017B.PDF ] | |
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