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74LVTH240SJ 반도체 회로 부품 판매점

Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs



Fairchild Semiconductor 로고
Fairchild Semiconductor
74LVTH240SJ 데이터시트, 핀배열, 회로
July 1999
Revised August 1999
74LVT240 • 74LVTH240
Low Voltage Octal Buffer/Line Driver
with 3-STATE Outputs
General Description
The LVT240 and LVTH240 are inverting octal buffers and
line drivers designed to be employed as memory address
drivers, clock drivers and bus oriented transmitters or
receivers which provides improved PC board density.
The LVTH240 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
These octal buffers and line drivers are designed for low-
voltage (3.3V) VCC applications, but with the capability to
provide a TTL interface to a 5V environment. The LVT240
and LVTH240 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH240), also
available without bushold feature (74LVT240).
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Outputs source/sink 32 mA/+64 mA
s Functionally compatible with the 74 series 240
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number Package Number
Package Description
74LVT240WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74LVT240SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVT240MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74LVT240MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LVTH240WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74LVTH240SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVTH240MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74LVTH240MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS500153
www.fairchildsemi.com


74LVTH240SJ 데이터시트, 핀배열, 회로
Connection Diagram
Pin Descriptions
Pin Names
OE1, OE2
I0–I7
O0–O7
Description
3-STATE Output
Enable Inputs
Inputs
3-STATE Outputs
Truth Tables
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Inputs
OE1
L
L
H
In
L
H
X
Inputs
OE2
L
L
H
In
L
H
X
Outputs
(Pins 12, 14, 16, 18)
H
L
Z
Outputs
(Pins 3, 5, 7, 9)
H
L
Z
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74LVTH240SJ driver

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74LVTH240SJ

Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs - Fairchild Semiconductor