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Fairchild Semiconductor |
June 1999
Revised June 1999
74LVT162240 • 74LVTH162240
Low Voltage 16-Bit Inverting Buffer/Line Driver
with 3-STATE Outputs and
25Ω Series Resistors in the Outputs
General Description
The LVT162240 and LVTH162240 contain sixteen inverting
buffers with 3-STATE outputs designed to be employed as
a memory and address driver, clock driver, or bus oriented
transmitter/receiver. The device is nibble controlled. Indi-
vidual 3-STATE control inputs can be shorted together for
8-bit or 16-bit operation.
The LVT162240 and LVTH162240 are designed with
equivalent 25Ω series resistance in both the HIGH and
LOW states of the output. This design reduces line noise in
applications such as memory address drivers, clock driv-
ers, and bus transceivers/transmitters.
The LVTH162240 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These inverting buffers and line drivers are designed for
low-voltage (3.3V) VCC applications, but with the capability
to provide a TTL interface to a 5V environment. The
LVT162240 and LVTH162240 are fabricated with an
advanced BiCMOS technology to achieve high speed oper-
ation similar to 5V ABT while maintaining a low power dis-
sipation.
Features
s Input and output interface capability to systems at
5V VCC
s Outputs include equivalent series resistance of 25Ω to
make external termination resistors unnecessary and
reduce overshoot and undershoot
s Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH162240),
also available without bushold feature (74LVT162240).
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s Functionally compatible with the 74 series 162240
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number Package Number
Package Description
74LVT162240MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LVT162240MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH162240MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LVTH162240MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
Description
OEn
I0–I15
O0–O15
Output Enable Inputs (Active LOW)
Inputs
3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS012490
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Connection Diagram
Truth Table
Inputs
OE1
I0–I3
LL
LH
HX
Inputs
OE2
I4–I7
LL
LH
HX
Inputs
OE3
I8–I11
LL
LH
HX
Inputs
OE4
L
L
H
I12–I15
L
H
X
Outputs
O0–O3
H
L
Z
Outputs
O4–O7
H
L
Z
Outputs
O8–O11
H
L
Z
Outputs
O12–O15
H
L
Z
H = HIGH Voltage Level
X = Immaterial
L = LOW Voltage Level
Z = High Impedance
Functional Description
The LVT162240 and LVTH162240 contain sixteen inverting
buffers with 3-STATE standard outputs. The device is nib-
ble (4 bits) controlled with each nibble functioning identi-
cally, but independent of the other. The control pins may be
shorted together to obtain full 16-bit operation. The 3-
Logic Diagram
STATE outputs are controlled by an Output Enable (OEn)
input for each nibble. When OEn is LOW, the outputs are in
2-state mode. When OEn is HIGH, the outputs are in the
high impedance mode, but this does not interfere with
entering new data into the inputs.
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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