74LVC322244A 반도체 회로 부품 판매점

32-bit buffer/line driver; with 30 ohm series termination resistors; 5 V input/output tolerant; 3-state



NXP Semiconductors 로고
NXP Semiconductors
74LVC322244A 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
DATA SHEET
74LVC322244A; 74LVCH322244A
32-bit buffer/line driver; with 30
series termination resistors; 5 V
input/output tolerant; 3-state
Product specification
File under Integrated Circuits, IC24
1999 Aug 31

74LVC322244A 데이터시트, 핀배열, 회로
Philips Semiconductors
Product specification
32-bit buffer/line driver; with 30 series termination 74LVC322244A;
resistors; 5 V input/output tolerant; 3-state
74LVCH322244A
FEATURES
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range of 1.2 to 3.6 V
CMOS low power consumption
MULTIBYTEflow-trough standard pin-out architecture
Low inductance multiple power and ground pins for
minimum noise and ground bounce
Direct interface with TTL levels
Bus hold on data inputs (74LVCH322244A only)
Integrated 30 termination resistors
Typical output ground bounce voltage:
VOLP <0.8 V at VCC = 3.3 V; Tamb = 25 °C
Typical output VOH undershoot voltage:
VOHV >2 V at VCC = 3.3 V; Tamb = 25 °C
Power-off disabled outputs, permitting live insertion
Plastic fine-pitch ball grid array package.
DESCRIPTION
The 74LVC(H)322244A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families. Inputs can be
driven from either 3.3 or 5 V devices. In 3-state operation,
outputs can handle 5 V. These features allow the use of
these devices in a mixed 3.3 and 5 V environment.
The 74LVC(H)322244A is a 32-bit non-inverting buffer/line
driver with 3-state outputs. The 3-state outputs are
controlled by the output enable inputs 1OE and 2OE.
A HIGH on input nOE causes the outputs to assume a
high-impedance OFF-state.
The 74LVC(H)322244A is designed with 30 series
termination resistors in both HIGH and LOW output stages
to reduce line noise.
To ensure the high-impedance state during power-up or
power-down, input nOE should be tied to VCC through a
pull-up resistor; the minimum value of the resistor is
determined by the current-sinking capability of the driver.
The 74LVCH322244A bus hold data input circuit
eliminates the need for external pull-up resistors to hold
unused or floating data inputs at a valid logic level (see
Fig.3).
QUICK REFERENCE DATA
Ground = 0 V; Tamb = 25 °C; tr = tf 2.5 ns.
SYMBOL
PARAMETER
tPHL/tPLH
CI
CPD
propagation delay nAn to nYn
input capacitance
power dissipation capacitance per
buffer
CONDITIONS
CL = 50 pF; VCC = 3.3 V
VI = GND to VCC; note 1
Note
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
Σ(CL × VCC2 × fo) = sum of the outputs.
TYPICAL
2.9
5.0
25
UNIT
ns
pF
pF
1999 Aug 31
2




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74LVC322244A driver

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