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PDF 74LCXZ16240MTD Data sheet ( Hoja de datos )
| Número de pieza | 74LCXZ16240MTD | |
| Descripción | Low Voltage 16-Bit Inverting Buffer/Line Driver with 5V Tolerant Inputs/Outputs (Preliminary) | |
| Fabricantes | Fairchild Semiconductor | |
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Preliminary
February 2000
Revised February 2000
74LCXZ16240
Low Voltage 16-Bit Inverting Buffer/Line Driver with
5V Tolerant Inputs/Outputs (Preliminary)
General Description
The LCXZ16240 contains sixteen inverting buffers with 3-
STATE outputs designed to be employed as a memory and
address driver, clock driver, or bus-oriented transmitter/
receiver. The device is nibble controlled. Each nibble has
separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
When VCC is between 0 and 1.5V, the LCXZ16240 is in the
high impedance state during power up or power down. This
places the outputs in the high impedance (Z) state prevent-
ing intermittent low impedance loading or glitching in bus
oriented applications.
The LCXZ16240 is designed for low voltage (2.7V or 3.3V)
VCC applications with capacity of interfacing to a 5V signal
environment.
The LCXZ16240 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Features
s 5V tolerant inputs and outputs
s Guaranteed power up/down high impedance
s Supports live insertion/withdrawal
s 2.7V–3.6V VCC specifications provided
s 4.5 ns tPD max (VCC = 3.3V), 20 µA ICC max
s ±24 mA output drive (VCC = 3.0V)
s Implements patented noise/EMI reduction circuitry
s Latch-up performance exceeds 500 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
Ordering Code:
Order Number Package Number
Package Description
74LCXZ16240MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LCXZ16240MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Logic Symbol
Pin Descriptions
Pin Names
OEn
I0–I15
O0–O15
Description
Output Enable Inputs (Active LOW)
Inputs
Outputs
© 2000 Fairchild Semiconductor Corporation DS500257
www.fairchildsemi.com
1 page  
AC LOADING and WAVEFORMS Generic for LCX Family
Preliminary
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
VI
6V for VCC = 3.3V, 2.7V
VCC * 2 for VCC = 2.5V
CL
50 pF
30 pF
Waveform for Inverting and Non-Inverting Functions
3-STATE Output High Enable and
Disable Times for Logic
Propagation Delay. Pulse Width and trec Waveforms
Setup Time, Hold Time and Recovery Time for Logic
3-STATE Output Low Enable and
Disable Times for Logic
trise and tfall
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, tR = tF = 3ns)
Symbol
Vmi
Vmo
Vx
Vy
3.3V ± 0.3V
1.5V
1.5V
VOL + 0.3V
VOH − 0.3V
VCC
2.7V
1.5V
1.5V
VOL + 0.3V
VOH − 0.3V
5 www.fairchildsemi.com
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