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Fairchild Semiconductor |
December 2013
74LCX540
Low Voltage Octal Buffer/Line Driver
with 5V Tolerant Inputs and Outputs
Features
■ 5V tolerant input and outputs
■ 2.3V–3.6V VCC specifications provided
■ 6.5ns tPD max. (VCC = 3.3V), 10µA ICC max.
■ Power down high impedance inputs and outputs
■ Supports live insertion/withdrawal(1)
■ Implements proprietary noise/ EMI reduction circuitry
■ Latch-up performance exceeds JEDEC 78 conditions
■ ESD performance
– Human body model > 2000V
– Machine model > 200V
■ Leadless DQFN package
Note:
1. To ensure the high impedance state during power up
or down, OE should be tied to VCC through a pull-up
resistor: the minimum value of the resistor is
determined by the current-sourcing capability of the
driver.
General Description
The LCX540 is an octal buffer/line driver designed to be
employed as a memory and address driver, clock driver
and bus oriented transmitter/receiver.
This device is similar in function to the LCX240 while
providing flow-through architecture (inputs on opposite
side from outputs). This pinout arrangement makes this
device especially useful as an output port for micropro-
cessors, allowing ease of layout and greater PC board
density.
The LCX540 is designed for low voltage (2.5V or 3.3V)
VCC applications with capability of interfacing to a 5V
signal environment. The LCX540 is fabricated with an
advanced CMOS technology to achieve high speed
operation while maintaining CMOS low power dissipa-
tion.
Ordering Information
Package
Order Number Number
Package Description
74LCX540WM
M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LCX540SJ
74LCX540BQX(2)
M20D
MLP20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN),
JEDEC MO-241, 2.5 x 4.5mm
74LCX540MSA
MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
74LCX540MTC
MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Note:
2. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1995 Fairchild Semiconductor Corporation
74LCX540 Rev. 1.7.1
www.fairchildsemi.com
Connection Diagrams
Pin Assignments for
SOIC, SOP, SSOP, TSSOP
OE1 1
I0 2
I1 3
I2 4
I3 5
I4 6
I5 7
I6 8
I7 9
GND 10
20 VCC
19 OE2
18 O0
17 O1
16 O2
15 O3
14 O4
13 O5
12 O6
11 O7
Logic Symbol
OE1
OE2
IEEE/IEC
&
EN
I0
I1
I2
I3
I4
I5
I6
I7
O0
O1
O2
O3
O4
O5
O6
O7
Pad Assignment for DQFN
OE1 VCC
1 20
I0 2
19 OE2
I1 3
18 O0
I2 4
17 O1
I3 5
16 O2
I4 6
15 O3
I5 7
14 O4
I6 8
13 O5
I7 9
12 O6
10 11
GND O7
(Top View)
(Bottom View)
Truth Table
OE1
L
H
X
L
Inputs
OE2
L
X
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Outputs
I On
HL
XZ
XZ
LH
Pin Descriptions
Pin Names
Description
OE1, OE2
I0–I7
O0–O7
3-STATE Output Enable Inputs
Inputs
Outputs
DAP
No Connect
Note: DAP (Die Attach Pad)
©1995 Fairchild Semiconductor Corporation
74LCX540 Rev. 1.7.1
2
www.fairchildsemi.com
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