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74LCX240SJ 반도체 회로 부품 판매점

Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs



Fairchild Semiconductor 로고
Fairchild Semiconductor
74LCX240SJ 데이터시트, 핀배열, 회로
February 1994
Revised April 1999
74LCX240
Low Voltage Octal Buffer/Line Driver with
5V Tolerant Inputs and Outputs
General Description
The LCX240 is an inverting octal buffer and line driver
designed to be employed as a memory address driver,
clock driver and bus oriented transmitter or receiver. The
device is designed for low voltage (2.5V or 3.3V) VCC appli-
cations with capability of interfacing to a 5V signal environ-
ment.
The LCX240 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s 5V tolerant inputs and outputs
s 2.3V–3.6V VCC specifications provided
s 6.5 ns tPD max (VCC = 3.3V), 10 µA ICC max
s Power-down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s ±24 mA output drive (VCC = 3.0V)
s Implements patented noise/EMI reduction circuitry
s Latch-up performance exceeds 500 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number Package Number
Package Description
74LCX240WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74LCX240SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX240MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74LCX240MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
Connection Diagram
© 1999 Fairchild Semiconductor Corporation DS011993.prf
www.fairchildsemi.com


74LCX240SJ 데이터시트, 핀배열, 회로
Pin Descriptions
Pin Names
OE1, OE2
I0–I7
O0–O7
Description
3-STATE Output Enable Inputs
Inputs
Outputs
Truth Tables
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Inputs
OE1
L
L
H
Inputs
OE2
L
L
H
In
L
H
X
In
L
H
X
Outputs
(Pins 12, 14, 16, 18)
H
L
Z
Outputs
(Pins 3, 5, 7, 9)
H
L
Z
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74LCX240SJ driver

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Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs - Fairchild Semiconductor