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QS5LV91955Q 반도체 회로 부품 판매점

3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER



Integrated Device Technology 로고
Integrated Device Technology
QS5LV91955Q 데이터시트, 핀배열, 회로
QS5LV919
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
3.3V LOW SKEW CMOS PLL
CLOCK DRIVER WITH
INTEGRATED LOOP FILTER
INDUSTRIALTEMPERATURERANGE
QS5LV919
FEATURES:
• 3.3V operation
• JEDEC compatible LVTTL level outputs
• Clock inputs are 5V tolerant
• < 300ps output skew, Q0–Q4
• 2xQ output, Q outputs, Q output, Q/2 output
• Outputs 3-state and reset while OE/RST low
• PLL disable feature for low frequency testing
• Internal loop filter RC network
• Functional equivalent to MC88LV915, IDT74FCT388915
• Positive or negative edge synchronization (PE)
• Balanced drive outputs ±24mA
• 160MHz maximum frequency (2xQ output)
• Available in QSOP and PLCC packages
DESCRIPTION:
The QS5LV919 Clock Driver uses an internal phase locked loop
(PLL) to lock low skew outputs to one of two reference clock inputs.
Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and
design ensure < 300 ps skew between the Q0-Q4, and Q/2 outputs.
The QS5LV919 includes an internal RC filter which provides excellent
jitter characteristics and eliminates the need for external components.
Various combinations of feedback and a divide-by-2 in the VCO path
allow applications to be customized for linear VCO operation over a
wide range of input SYNC frequencies. The PLL can also be disabled
by the PLL_EN signal to allow low frequency or DC testing. The LOCK
output asserts to indicate when phase lock has been achieved. The
QS5LV919 is designed for use in high-performance workstations, multi-
board computers, networking hardware, and mainframe systems. Sev-
eral can be used in parallel or scattered throughout a system for guar-
anteed low skew, system-wide clock distribution networks.
For more information on PLL clock driver products, see Application
Note AN-227.
FUNCTIONAL BLOCK DIAGRAM
O E /R S T
SYNC0
SYNC1
REF_SEL
0
LOCK PE
FEEDBACK
1
PHASE
LOOP
DETECTOR
FILTER
VCO
PLL_EN
FREQ_SEL
01
1 /2 0
RDR DR DRDR DR DRD
Q Q Q Q Q Q QQ
Q /2 Q5 Q4 Q3
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
c 2001 Integrated Device Technology, Inc.
1
Q2
Q1 Q0
2xQ
JULY 2001
DSC-5820/3


QS5LV91955Q 데이터시트, 핀배열, 회로
QS5LV919
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
PIN CONFIGURATION
INDUSTRIALTEMPERATURERANGE
GND
Q5
VDD
OE/RST
FEEDBACK
REF_SEL
SYNC0
AVDD
PE
AGND
SYNC1
FREQ_SEL
GND
Q0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 Q4
27 VDD
26 2xQ
25 Q/2
24 GND
23 Q3
22 VDD
21 Q2
20 GND
19 LOCK
18 PLL_EN
17 GND
16 Q1
15 VDD
4 3 2 1 28 27 26
FEEDBACK 5
25 Q/2
REF_SEL 6
24 GND
SYNC0 7
23 Q3
AVDD 8
22 VDD
PE 9
21 Q2
AGND 10
20 GND
SYNC1 11
19 LOCK
12 13 14 15 16 17 18
QSOP
TOP VIEW
PLCC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS (1)
Symbol Rating
Max. Unit
VDD, AVDD Supply Voltage to Ground
–0.5 to +7
V
DC Input Voltage VIN
–0.5 to +5.5
V
Maximum Power
QSOP
655
mW
Dissipation (TA = 85°C) PLCC 770 mW
TSTG StorageTemperatureRange
–65 to +150
°C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = 25°C, f = 1MHz, VIN = 0V)
QSOP
PLCC
Parameter Typ.
Max.
Typ.
Max.
CIN 3 4 4 6
Unit
pF
2




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QS5LV91955Q driver

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3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER - Integrated Device Technology



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3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER - Integrated Device Technology