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IR2103S 반도체 회로 부품 판매점

HALF-BRIDGE DRIVER



International Rectifier 로고
International Rectifier
IR2103S 데이터시트, 핀배열, 회로
Data Sheet No. PD60045-N
IR2103(S)
HALF-BRIDGE DRIVER
Features
Floating channel designed for bootstrap operation
Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune
Gate drive supply range from 10 to 20V
Undervoltage lockout
3.3V, 5V and 15V logic compatible
Cross-conduction prevention logic
Matched propagation delay for both channels
Internal set deadtime
High side output in phase with HIN input
Low side output out of phase with LIN input
Product Summary
VOFFSET
600V max.
IO+/-
130 mA / 270 mA
VOUT
10 - 20V
ton/off (typ.)
680 & 150 ns
Deadtime (typ.)
520 ns
Packages
Description
The IR2103(S) are high voltage, high speed power
MOSFET and IGBT drivers with dependent high and
low side referenced output channels.Proprietary HVIC
8-Lead SOIC
and latch immune CMOS technologies enable rug-
gedized monolithic construction. The logic input is
compatible with standard CMOS or LSTTL output,
IR2103S
8-Lead PDIP
IR2103
down to 3.3V logic. The output drivers feature a high
pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to
drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 volts.
Typical Connection
up to 600V
VCC
VCC
VB
HIN HIN HO
LIN LIN VS
COM
LO
TO
LOAD
(Refer to Lead Assignments for correct configuration). This/These diagram(s) show electrical connections only.
Please refer to our Application Notes and DesignTips for proper circuit board layout.
www.irf.com
1


IR2103S 데이터시트, 핀배열, 회로
IR2103(S)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
Symbol
VB
VS
VHO
VCC
VLO
VIN
dVs/dt
PD
RthJA
TJ
TS
TL
Definition
High side floating absolute voltage
High side floating supply offset voltage
High side floating output voltage
Low side and logic fixed supply voltage
Low side output voltage
Logic input voltage (HIN & LIN)
Allowable offset supply voltage transient
Package power dissipation @ TA +25°C
Thermal resistance, junction to ambient
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
(8 Lead PDIP)
(8 Lead SOIC)
(8 Lead PDIP)
(8 Lead SOIC)
Min.
-0.3
VB - 25
VS - 0.3
-0.3
-0.3
-0.3
-55
Max.
625
VB + 0.3
VB + 0.3
25
VCC + 0.3
VCC + 0.3
50
1.0
0.625
125
200
150
150
300
Units
V
V/ns
W
°C/W
°C
Recommended Operating Conditions
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The VS offset rating is tested with all supplies biased at 15V differential.
Symbol
VB
VS
VHO
VCC
VLO
VIN
TA
Definition
High side floating supply absolute voltage
High side floating supply offset voltage
High side floating output voltage
Low side and logic fixed supply voltage
Low side output voltage
Logic input voltage (HIN & LIN)
Ambient temperature
Min.
VS + 10
Note 1
VS
10
0
0
-40
Max.
VS + 20
600
VB
20
VCC
VCC
125
Units
V
°C
Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS. (Please refer to the Design Tip
DT97-3 for more details).
2 www.irf.com




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