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International Rectifier |
Data Sheet No. PD60195-D
IR2010(S) & (PbF)
Features
HIGH AND LOW SIDE DRIVER
• Floating channel designed for bootstrap operation Product Summary
Fully operational to 200V
Tolerant to negative transient voltage, dV/dt immune
• Gate drive supply range from 10 to 20V
• Undervoltage lockout for both channels
• 3.3V logic compatible
VOFFSET
IO+/-
200V max.
3.0A / 3.0A typ.
Separate logic supply range from 3.3V to 20V
Logic and power ground ±5V offset
• CMOS Schmitt-triggered inputs with pull-down
• Shut down input turns off both channels
• Matched propagation delay for both channels
• Outputs in phase with inputs
• Also available LEAD-FREE
VOUT
ton/off
Delay Matching
10 - 20V
95 & 65 ns typ.
15 ns max.
Applications
• Audio Class D amplifiers
• High power DC-DC SMPS converters
• Other high frequency applications
Description
The IR2010 is a high power, high voltage, high speed power MOSFET and IGBT
drivers with independent high and low side referenced output channels, ideal for Audio
Class D and DC-DC converter applications. Logic inputs are compatible with standard
CMOS or LSTTL output, down to 3.0V logic. The output drivers feature a high pulse
current buffer stage designed for minimum driver cross-conduction. Propagation de-
lays are matched to simplify use in high frequency applications. The floating channel
can be used to drive an N-channel power MOSFET or IGBT in the high side configura-
tion which operates up to 200 volts. Proprietary HVIC and latch immune CMOS tech-
nologies enable ruggedized monolithic construction.
Packages
14-Lead PDIP
16-Lead SOIC
Typical Connection
200V
HO
VDD
VDD
VB
HIN HIN VS
SD SD
LIN LIN VCC
VSS VSS COM
VCC LO
(Refer to Lead Assignments for correct configuration). This/These diagram(s) show electrical connections only.
Please refer to our Application Notes and DesignTips for proper circuit board layout.
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TO
LOAD
1
IR2010(S) & (PbF)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
Symbol
VB
VS
VHO
VCC
VLO
VDD
VSS
VIN
dVs/dt
PD
RTHJA
TJ
TS
TL
Definition
High side floating supply voltage
High side floating supply offset voltage
High side floating output voltage
Low side fixed supply voltage
Low side output voltage
Logic supply voltage
Logic supply offset voltage
Logic input voltage (HIN, LIN & SD)
Allowable offset supply voltage transient (figure 2)
Package power dissipation @ TA ≤ +25°C (14 lead DIP)
(16 lead SOIC)
Thermal resistance, junction to ambient
(14 lead DIP)
(16 lead SOIC)
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
Min.
-0.3
VB - 25
VS - 0.3
-0.3
-0.3
-0.3
VCC - 25
VSS - 0.3
—
—
—
—
—
—
-55
—
Max.
225
VB + 0.3
VB + 0.3
25
VCC + 0.3
VSS + 25
VCC + 0.3
VDD + 0.3
50
1.6
1.25
75
100
150
150
300
Units
V
V/ns
W
°C/W
°C
Recommended Operating Conditions
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15V differential. Typical
ratings at other bias conditions are shown in figures 24 and 25.
Symbol
Definition
Min.
Max. Units
VB
VS
VHO
VCC
VLO
VDD
VSS
VIN
TA
High side floating supply absolute voltage
High side floating supply offset voltage
High side floating output voltage
Low side fixed supply voltage
Low side output voltage
Logic supply voltage
Logic supply offset voltage
Logic input voltage (HIN, LIN & SD)
Ambient temperature
VS + 10
Note 1
VS
10
0
VSS + 3
-5 (Note 2)
VSS
-40
VS + 20
200
VB
20
VCC
VSS + 20
5
VDD
125
V
°C
Note 1: Logic operational for VS of -4 to +200V. Logic state held for VS of -4V to -VBS.
Note 2: When VDD < 5V, the minimum VSS offset is limited to -VDD.
(Please refer to the Design Tip DT97-3 for more details).
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