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PDF 74ABT541CPC Data sheet ( Hoja de datos )
| Número de pieza | 74ABT541CPC | |
| Descripción | Octal Buffer/Line Driver with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
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September 1992
Revised November 1999
74ABT541
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The ABT541 is an octal buffer and line driver with 3-STATE
outputs designed to be employed as a memory and
address driver, clock driver, or bus-oriented transmitter/
receiver. The ABT541 is similar to the ABT244 with broad-
side pinout.
Features
s Non-inverting buffers
s Output sink capability of 64 mA, source capability of
32 mA
s Guaranteed output skew
s Guaranteed multiple output switching specifications
s Output switching specified for both 50 pF and 250 pF
loads
s Guaranteed simultaneous switching, noise level and
dynamic threshold performance
s Guaranteed latchup protection
s High impedance, glitch free bus loading during entire
power up and power down cycle
s Nondestructive hot insertion capability
s Flow-through pinout for ease of PC board layout
s Disable time less than enable time to avoid bus
contention
Ordering Code:
Order Number Package Number
Package Description
74ABT541CSC
74ABT541CSJ
74ABT541CMSA
74ABT541CMTC
74ABT541CPC
M20B
M20D
MSA20
MTC20
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending suffix “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
Description
OE1, OE2
I0–I7
O0–O7
Output Enable Input (Active LOW)
Inputs
Outputs
Truth Table
Inputs
OE1
OE2
LL
HX
XH
LL
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
I
H
X
X
L
Outputs
H
Z
Z
L
© 1999 Fairchild Semiconductor Corporation DS011501
www.fairchildsemi.com
1 page  
AC Loading
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
FIGURE 2. Test Input Signal Levels
Amplitude Rep. Rate
tW
tr
tf
3.0V
1 MHz 500 ns 2.5 ns 2.5 ns
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
FIGURE 6. 3-STATE Output HIGH and LOW
Enable and Disable Time
FIGURE 5. Propagation Delay, Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time and
Recovery Time Waveforms
5 www.fairchildsemi.com
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74ABT541CPC.PDF ] | |
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