파트넘버.co.kr 74C2525 데이터시트 PDF


74C2525 반도체 회로 부품 판매점

1-to-8 Minimum Skew Clock Driver



National Semiconductor 로고
National Semiconductor
74C2525 데이터시트, 핀배열, 회로
September 1995
CGS74C2525  CGS74CT2525
CGS74C2526  CGS74CT2526
1-to-8 Minimum Skew Clock Driver
The CGS ’C CT2525 is a minimum skew clock driver with
one input driving eight outputs specifically designed for sig-
nal generation and clock distribution applications The ’2525
is designed to distribute a single clock to eight separate
receivers with low skew across all outputs during both the
tPLH and tPHL transitions The ’2526 is similar to the ’2525
but contains a multiplexed clock input to allow for systems
with dual clock speeds or systems where a separate test
clock has been implemented
Features
Y These CGS devices implement National’s FACTTM
family
Y Ideal for signal generation and clock distribution
Y Guaranteed pin to pin and part to part skew
Y Multiplexed clock input (’2526)
Y Guaranteed 2 kV minimum ESD protection
Y Symmetric output current drive of 24 mA for IOL IOH
Y ’CT has TTL-compatible inputs
Y These products are identical to 74AC ACT2525 and
2526
Y Available as Mil Aero versions
54AC ACT2525
54AC ACT2526
Logic Symbols
’2525
Connection Diagrams
Pin Assignment
for DIP and SOIC
’2525
’2526
TL F 10684 – 1
TL F 10684 – 2
’2526
TL F 10684 – 3
TRI-STATE is a registered trademark of National Semiconductor Corporation
FACTTM is a trademark of National Semiconductor Corporation
C1996 National Semiconductor Corporation TL F 10684
RRD-B30M106 Printed in U S A
TL F 10684 – 4
http www national com


74C2525 데이터시트, 핀배열, 회로
Functional Description
On the multiplexed clock device the SEL pin is used to
determine which CLKn input will have an active effect on
the outputs of the circuit When SEL e 1 the CLK1 input is
selected and when SEL e 0 the CLK0 input is selected
The non-selected CLKn input will not have any effect on the
logical output level of the circuit The output pins act as a
single entity and will follow the state of the CLK or
CLK1 CLK0 pins when either the multiplexed (’2526) or the
straight (’2525) clock distribution chip is selected
Pin Description
Pin Names
Description
CLK
CLK0 CLK1
O0 – O7
SEL
Clock Input (’2525)
Clock Inputs (’2526)
Outputs
Clock Select (’2526)
’2525
Truth Tables
’2525
Inputs
Outputs
CLK
L
H
O0 – O7
L
H
’2526
Inputs
CLK0 CLK1 SEL
L XL
H XL
X LH
X HH
L e Low Voltage Level
H e High Voltage Level
X e Immaterial
Outputs
O0 – O7
L
H
L
H
’2526
TL F 10684–7
TL F 10684 – 8
http www national com
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74C2525 driver

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