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74AVC16834 반도체 회로 부품 판매점

18-bit registered driver with inverted register enable 3-State



NXP Semiconductors 로고
NXP Semiconductors
74AVC16834 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
74AVC16834
18-bit registered driver
with inverted register enable (3-State)
Preliminary specification
Replaces datasheet 74AVC16834/74AVCH16834 dated 1998 Dec 11
1999 Jul 23
Philips
Semiconductors


74AVC16834 데이터시트, 핀배열, 회로
Philips Semiconductors
18-bit registered driver with inverted register enable
(3-State)
Preliminary specification
74AVC16834
FEATURES
Wide supply voltage range of 1.2 V to 3.6 V
Complies with JEDEC standard no. 8-1A/5/7.
CMOS low power consumption
Input/output tolerant up to 3.6 V
DCO (Dynamic Controlled Output) circuit dynamically changes
output impedance, resulting in noise reduction without speed
degradation
Low inductance multiple VCC and GND pins for minimum noise
and ground bounce
Power off disables 74AVC16834 outputs, permitting Live Insertion
DESCRIPTION
The 74AVC16834 is a 18-bit universal bus driver. Data flow is
controlled by output enable (OE), latch enable (LE) and clock inputs
(CP).
This product is designed to have an extremely fast propagation
delay and a minimum amount of power consumption.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor (Live
Insertion).
A Dynamic Controlled Output (DCO) circuitry is implemented to
support termination line drive during transient. See the graphs on
page 8 for typical curves.
PIN CONFIGURATION
NC
NC
Y0
GND
Y1
Y2
VCC
Y3
Y4
Y5
GND
Y6
Y7
Y8
Y9
Y10
Y11
GND
Y12
Y13
Y14
VCC
Y15
Y16
GND
Y17
OE
LE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 GND
55 NC
54 A0
53 GND
52 A1
51 A2
50 VCC
49 A3
48 A4
47 A5
46 GND
45 A6
44 A7
43 A8
42 A9
41 A10
40 A11
39 GND
38 A12
37 A13
36 A14
35 VCC
34 A15
33 A16
32 GND
31 A17
30 CP
29 GND
SH00156
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf 2.0 ns; CL = 30 pF.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
tPHL/tPLH
Propagation delay
An to Yn
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
2.6
2.0
1.7
tPHL/tPLH
Propagation delay
LE to Yn;
CP to Yn
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
2.9
2.3
1.9
CI Input capacitance
CPD
Power dissipation capacitance per buffer
VI = GND to VCC1
Outputs enabled
Output disabled
5.0
25
6
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.
UNIT
ns
ns
pF
pF
ORDERING INFORMATION
PACKAGES
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II
TEMPERATURE
RANGE
–40°C to +85°C
ORDER CODE
74AVC16834 DGG
DRAWING
NUMBER
SOT364-1
1999 Jul 23
2




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74AVC16834 driver

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