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74ALVCH16827DGG 반도체 회로 부품 판매점

20-bit buffer/line driver/ non-inverting 3-State



NXP Semiconductors 로고
NXP Semiconductors
74ALVCH16827DGG 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
74ALVCH16827
20-bit buffer/line driver, non-inverting
(3-State)
Product specification
IC24 Data Handbook
1998 Jul 27
Philips
Semiconductors


74ALVCH16827DGG 데이터시트, 핀배열, 회로
Philips Semiconductors
20-bit buffer/line driver, non-inverting (3-State)
Product specification
74ALVCH16827
FEATURES
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A
Wide supply voltage range of 1.2V to 3.6V
CMOS low power consumption
Direct interface with TTL levels
Universal bus transceiver with D-type latches and D-type flip-flops
capable of operating in transparent, latched, clocked or
clocked-enabled mode.
MULTIBYTETM flow-through standard pin-out architecture
Low inductance multiple VCC and GND pins for minimum noise
and ground bounce
Current drive ±24 mA at 3.0 V
All inputs have bus hold circuitry
Output drive capability 50transmission lines @ 85°C
3-State non-inverting outputs for bus oriented applications
DESCRIPTION
The 74ALVCH16827 is a 20-bit non-inverting buffer/driver with
3-State outputs for bus oriented applications.
The 74ALVCH16827 consists of two 10-bit sections with separate
output enable signals. For either 10-bit buffer section, the two output
enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be
active. If either output enable input is high, the outputs of that 10-bit
buffer section are in high impedance state.
The 74ALVCH16827 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf = 2.5ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
CI
CPD
Propagation delay
CP to Qn
Input capacitance
Power dissipation capacitance per latch
VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF
VI = GND to VCC1
Output enabled
Output disabled
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in mW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
S (CL × VCC2 × fo) = sum of outputs.
TYPICAL
2.0
2.0
5
20
3
UNIT
ns
pF
pF
ORDERING INFORMATION
PACKAGES
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
–40°C to +85°C
74ALVCH16827 DGG
NORTH AMERICA
ACH16827 DGG
DWG NUMBER
SOT364-1
PIN DESCRIPTION
PIN NUMBER
55, 54, 52, 51, 49, 48, 47, 45, 44, 43,
42, 41, 40, 38, 37, 36, 34, 33, 31, 30
2, 3, 5, 6, 8, 9, 10, 12, 13, 14,
15, 16, 17, 19, 20, 21, 23, 24, 26, 27
1, 56,
28, 29
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
SYMBOL
1A0 - 1A9
2A0 - 2A9
1Y0 - 1Y9
2Y0 - 2Y9
1OE0, 1OE1
2OE0, 2OE1
GND
VCC
Data inputs
FUNCTION
Data outputs
Output enable inputs (active-Low)
Ground (0V)
Positive supply voltage
1998 Jul 27
2 853-2096 19785




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20-bit buffer/line driver/ non-inverting 3-State - NXP Semiconductors