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PDF 74ALVCH16240T Data sheet ( Hoja de datos )
| Número de pieza | 74ALVCH16240T | |
| Descripción | Low Voltage 16-Bit Inverting Buffer/Line Driver with Bushold | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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September 2001
Revised February 2002
74ALVCH16240
Low Voltage 16-Bit Inverting Buffer/Line Driver
with Bushold
General Description
The ALVCH16240 contains sixteen inverting buffers with
3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The ALVCH16240 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating inputs at a valid logic level.
The 74ALVCH16240 is designed for low voltage (1.65V to
3.6V) VCC applications with output capability up to 3.6V.
The 74ALVCH16240 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.65V to 3.6V VCC supply operation
s 3.6V tolerant control inputs and outputs
s Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
s tPD
3.9 ns max for 3.0V to 3.6V VCC
5.3 ns max for 2.3V to 2.7V VCC
6.0 ns max for 1.65V to 1.95V VCC
s Uses patented noise/EMI reduction circuitry
s Latch-up conforms to JEDEC JED78
s ESD performance:
Human body model > 2000V
Machine model > 200V
Ordering Code:
Order Number
Package
Number
Package Descriptions
74ALVCH16240T
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OEn
I0–I15
O0–O15
Description
Output Enable Input (Active LOW)
Bushold Inputs
Outputs
© 2002 Fairchild Semiconductor Corporation DS500629
www.fairchildsemi.com
1 page  
AC Loading and Waveforms
TABLE 1. Values for Figure 1
TEST
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
SWITCH
Open
VL
GND
FIGURE 1. AC Test Circuit
TABLE 2. Variable Matrix
(Input Characteristics: f = 1MHz; tr = tf = 2ns; Z0 = 50Ω)
Symbol
Vmi
Vmo
VX
VY
VL
3.3V ± 0.3V
1.5V
1.5V
VOL + 0.3V
VOH − 0.3V
6V
2.7V
1.5V
1.5V
VOL + 0.3V
VOH − 0.3V
6V
VCC
2.5V ± 0.2V
VCC/2
VCC/2
VOL + 0.15V
VOH − 0.15V
VCC*2
1.8V ± 0.15V
VCC/2
VCC/2
VOL + 0.15V
VOH − 0.15V
VCC*2
FIGURE 2. Waveform for Inverting and Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
5 www.fairchildsemi.com
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| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet 74ALVCH16240T.PDF ] | |
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