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74ALVCH162244 반도체 회로 부품 판매점

Low Voltage 16-Bit Buffer/Line Driver with Bushold and 26 Series Resistor in Outputs



Fairchild Semiconductor 로고
Fairchild Semiconductor
74ALVCH162244 데이터시트, 핀배열, 회로
September 2001
Revised February 2002
74ALVCH162244
Low Voltage 16-Bit Buffer/Line Driver with Bushold
and 26Series Resistor in Outputs
General Description
The ALVCH162244 contains sixteen non-inverting buffers
with 3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The ALVCH162244 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level
The 74ALVCH162244 is also designed with 26series
resistors in the outputs. This design reduces line noise in
applications such as memory address drivers, clock driv-
ers, and bus transceivers/transmitters.
The 74ALVCH162244 is designed for low voltage (1.65V to
3.6V) VCC applications with output capability up to 3.6V.
The 74ALVCH162244 is fabricated with an advanced
CMOS technology to achieve high speed operation while
maintaining low CMOS power dissipation.
Features
s 1.65V to 3.6V VCC supply operation
s 3.6V tolerant control inputs and outputs
s Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
s 26series resistors in outputs
s tPD
4.2 ns max for 3.0V to 3.6V VCC
4.9 ns max for 2.3V to 2.7V VCC
7.6 ns max for 1.65V to 1.95V VCC
s Uses patented noise/EMI reduction circuitry
s Latch-up conforms to JEDEC JED78
s ESD performance:
Human body model > 2000V
Machine model > 200V
Ordering Code:
Order Number
Package
Number
Package Description
74ALVCH162244T
MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OEn
I0I15
O0O15
Description
Output Enable Input (Active LOW)
Bushold Inputs
Outputs
© 2002 Fairchild Semiconductor Corporation DS500632
www.fairchildsemi.com


74ALVCH162244 데이터시트, 핀배열, 회로
Connection Diagram
Truth Tables
Inputs
OE1
L
L
H
I0–I3
L
H
X
Outputs
O0–O3
L
H
Z
Inputs
OE2
L
L
H
I4–I7
L
H
X
Outputs
O4–O7
L
H
Z
Inputs
OE3
L
L
H
I8–I11
L
H
X
Outputs
O8–O11
L
H
Z
Inputs
Outputs
OE4
I12–I15
O12–O15
LLL
L HH
HX Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
Functional Description
The 74ALVCH162244 contains sixteen non-inverting buffers with 3-STATE outputs. The device is nibble (4 bits) controlled
with each nibble functioning identically, but independent of each other. The control pins may be shorted together to obtain
full 16-bit operation.The 3-STATE outputs are controlled by an Output Enable (OEn) input. When OEn is LOW, the outputs
are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not inter-
fere with entering new data into the inputs.
Logic Diagram
www.fairchildsemi.com
2




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74ALVCH162244 driver

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