74ALVC16334A 반도체 회로 부품 판매점

16-bit registered driver with inverted register enable 3-State



NXP Semiconductors 로고
NXP Semiconductors
74ALVC16334A 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
74ALVC16334A
16-bit registered driver with inverted
register enable (3-State)
Product specification
Replaces datasheet 74ALVC16334 of 2000 Jan 04
IC24 Data Handbook
2000 Mar 14
Philips
Semiconductors

74ALVC16334A 데이터시트, 핀배열, 회로
Philips Semiconductors
16-bit registered driver with inverted register enable
(3-State)
Product specification
74ALVC16334A
FEATURES
Wide supply voltage range of 1.2 V to 3.6 V
Complies with JEDEC standard no. 8-1A.
CMOS low power consumption
Direct interface with TTL levels
Current drive ± 24 mA at 3.0 V
MULTIBYTETM flow-through standard pin-out architecture
Low inductance multiple VCC and GND pins for minimum noise
and ground bounce
Output drive capability 50 transmission lines @ 85°C
Input diodes to accommodate strong drivers
DESCRIPTION
The 74ALVC16334A is a 16–bit universal bus driver. Data flow is
controlled by active low output enable (OE), active low latch enable
(LE) and clock inputs (CP).
When LE is LOW, the A to Y data flow is transparent. When LE is
HIGH and CP is held at LOW or HIGH, the data is latched; on the
LOW to HIGH transient of CP the A-data is stored in the
latch/flip-flop.
When OE is LOW the outputs are active. When OE is HIGH, the
outputs go to the high impedance OFF-state. Operation of the OE
input does not affect the state of the latch/flip-flop.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
PIN CONFIGURATION
OE
Y1
Y2
GND
Y3
Y4
VCC
Y5
Y6
GND
Y7
Y8
Y9
Y10
GND
Y11
Y12
VCC
Y13
Y14
GND
Y15
Y16
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 CP
47 A1
46 A2
45 GND
44 A3
43 A4
42 VCC
41 A5
40 A6
39 GND
38 A7
37 A8
36 A9
35 A10
34 GND
33 A11
32 A12
31 VCC
30 A13
29 A14
28 GND
27 A15
26 A16
25 LE
SH00198
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
tPHL/tPLH
Propagation delay
An to Yn;
LE to Yn;
CP to Yn
VCC = 3.3 V, CL = 50 pF
2.3
2.6
2.5
Fmax
CI
CI/O
CPD
Maximum clock frequency
Input capacitance
Input/Output capacitance
Power dissipation capacitance per buffer
VCC = 3.3 V, CL = 50 pF
VI = GND to VCC1
transparent mode
Output enabled
Output disabled
Clocked mode
Output enabled
Output disabled
350
4.0
8.0
13
3
22
15
NOTE:
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.
UNIT
ns
MHz
pF
pF
pF
2000 Mar 14
2 853–2196 23314




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74ALVC16334A driver

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