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74ALVC162835 반도체 회로 부품 판매점

Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26 Series Resistors in Outputs



Fairchild Semiconductor 로고
Fairchild Semiconductor
74ALVC162835 데이터시트, 핀배열, 회로
September 2001
Revised February 2002
74ALVC162835
Low Voltage 18-Bit Universal Bus Driver
with 3.6V Tolerant Inputs/Outputs
and 26Series Resistors in Outputs
General Description
The ALVC162835 low voltage 18-bit universal bus driver
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched and clocked modes.
Data flow is controlled by output-enable (OE), latch-enable
(LE), and clock (CLK) inputs. The device operates in
Transparent Mode when LE is held HIGH. The device
operates in clocked mode when LE is LOW and CLK is tog-
gled. Data transfers from the Inputs (In) to Outputs (On) on
a Positive Edge Transition of the Clock. When OE is LOW,
the output data is enabled. When OE is HIGH the output
port is in a high impedance state.
The ALVC162835 is designed with 26series resistors in
the outputs. This design reduces noise in applications such
as memory address drivers, clock drivers, and bus trans-
ceivers/transmitters.
The 74ALVC162835 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O capability up to 3.6V.
The 74ALVC162835 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s Compatible with PC100 DIMM module specifications
s 1.65V to 3.6V VCC specifications provided
s 3.6V tolerant inputs and outputs
s 26series resistors in outputs
s tPD (CLK to On)
5.4 ns max for 3.0V to 3.6V VCC
6.3 ns max for 2.3V to 2.7V VCC
9.2 ns max for 1.65V to 1.95V VCC
s Power-off high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s Latchup conforms to JEDEC JED78
s ESD performance:
Human body model > 2000V
Machine model >200V
Note 1: To ensure the high impedance state during power up or power
down, OE should be tied to VCC through a pulldown resistor; the minimum
value of the resistor is determined by the current sourcing capability of the
driver.
Ordering Code:
Order Number
Package
Number
Package Description
74ALVC162835T
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2002 Fairchild Semiconductor Corporation DS500646
www.fairchildsemi.com


74ALVC162835 데이터시트, 핀배열, 회로
Connection Diagram
Logic Diagram
Pin Descriptions
Pin Names
OE
LE
CLK
I1 - I18
O1 - O18
Description
Output Enable Input (Active LOW)
Latch Enable Input
Clock Input
Data Inputs
3-STATE Outputs
Truth Table
Inputs
Outputs
OE LE CLK In
On
HXXX
Z
LHX L
L
LHXH
H
LLL
L
L L H
H
L LH
LLL
H = Logic HIGH
L = Logic LOW
X = Dont Care, but not floating
Z = High Impedance
↑ = LOW-to-HIGH Clock Transition
X O0 (Note 2)
X O0 (Note 3)
Note 2: Output level before the indicated steady-state input conditions
were established provided that CLK was HIGH before LE went LOW.
Note 3: Output level before the indicated steady-state input conditions
were established.
www.fairchildsemi.com
2




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74ALVC162835 driver

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