74ALVC16240 반도체 회로 부품 판매점

Low Voltage 16-Bit Inverting Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs



Fairchild Semiconductor 로고
Fairchild Semiconductor
74ALVC16240 데이터시트, 핀배열, 회로
October 2001
Revised October 2001
74ALVC16240
Low Voltage 16-Bit Inverting Buffer/Line Driver
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16240 contains sixteen inverting buffers with 3-
STATE outputs to be employed as a memory and address
driver, clock driver, or bus oriented transmitter/receiver.
The device is nibble (4-bit) controlled. Each nibble has sep-
arate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The 74ALVC16240 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O capability up to 3.6V.
The 74ALVC16240 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.65V to 3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s tPD
3.0 ns max for 3.0V to 3.6V VCC
3.5 ns max for 2.3V to 2.7V VCC
6.0 ns max for 1.65V to 1.95V VCC
s Power-off high impedance inputs and outputs
s Supports live insertion and withdrawal (Note 1)
s Uses patented noise/EMI reduction circuitry
s Latchup conforms to JEDEC JED78
s ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Descriptions
74ALVC16240MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OEn
I0I15
O0O15
Description
Output Enable Input (Active LOW)
Inputs
Outputs
© 2001 Fairchild Semiconductor Corporation DS500689
www.fairchildsemi.com

74ALVC16240 데이터시트, 핀배열, 회로
Connection Diagram
Truth Tables
Inputs
OE1
L
L
H
I0–I3
L
H
X
Outputs
O0–O3
H
L
Z
Inputs
OE2
L
L
H
I4–I7
L
H
X
Outputs
O4–O7
H
L
Z
Inputs
OE3
L
L
H
I8–I11
L
H
X
Outputs
O8–O11
H
L
Z
Functional Description
The 74ALVC16240 contains sixteen inverting buffers with
3-STATE outputs. The device is nibble (4 bits) controlled
with each nibble functioning identically, but independent of
each other. The control pins may be shorted together to
obtain full 16-bit operation.The 3-STATE outputs are con-
Logic Diagram
Inputs
Outputs
OE4
I12–I15
LL
LH
HX
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
O12–O15
H
L
Z
trolled by an Output Enable (OEn) input. When OEn is
LOW, the outputs are in the 2-state mode. When OEn is
HIGH, the standard outputs are in the high impedance
mode but this does not interfere with entering new data into
the inputs.
www.fairchildsemi.com
2




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74ALVC16240 driver

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