74ALVC162244GX 반도체 회로 부품 판매점
Low Voltage 16-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs and 26 Series Resistor in Outputs
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 Fairchild Semiconductor |
November 2001
Revised November 2001
74ALVC162244
Low Voltage 16-Bit Buffer/Line Driver
with 3.6V Tolerant Inputs and Outputs
and 26Ω Series Resistor in Outputs
General Description
The ALVC162244 contains sixteen non-inverting buffers
with 3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The 74ALVC162244 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O capability up to 3.6V. The
74ALVC162244 is also designed with 26Ω series resistors
in the outputs. This design reduces line noise in applica-
tions such as memory address drivers, clock drivers, and
bus transceivers/transmitters.
The 74ALVC162244 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.65V to 3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s 26Ω series resistors in outputs
s tPD
3.8 ns max for 3.0V to 3.6V VCC
4.3 ns max for 2.3V to 2.7V VCC
7.6 ns max for 1.65V to 1.95V VCC
s Power-off high impedance inputs and outputs
s Supports live insertion and withdrawal
s Uses patented noise/EMI reduction circuitry
s Latchup conforms to JEDEC JED78
s ESD performance:
Human body model > 2000V
Machine model > 200V
s Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74ALVC162244GX
(Note 2)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
74ALVC162244T
(Note 3)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2: BGA package available in Tape and Reel only.
Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
© 2001 Fairchild Semiconductor Corporation DS500696
www.fairchildsemi.com
Logic Symbol
Connection Diagrams
Pin Assignment for TSSOP
Pin Assignment for FBGA
(Top Thru View)
www.fairchildsemi.com
Pin Descriptions
Pin Names
OEn
I0–I15
O0–O15
NC
Description
Output Enable Input (Active LOW)
Inputs
Outputs
No Connect
FBGA Pin Assignments
12
A O0 NC
B O2 O1
C O4 O3
D O6 O5
E O8 O7
F O10 O9
G
O12
O11
H O14 O13
J O15 NC
Truth Tables
3
OE1
NC
VCC
GND
GND
GND
VCC
NC
OE4
4
OE2
NC
VCC
GND
GND
GND
VCC
NC
OE3
5
NC
I1
I3
I5
I7
I9
I11
I13
NC
6
I0
I2
I4
I6
I8
I10
I12
I14
I15
Inputs
OE1
L
L
H
I0–I3
L
H
X
Inputs
OE2
L
L
H
I4–I7
L
H
X
Inputs
OE3
L
L
H
I8–I11
L
H
X
Outputs
O0–O3
L
H
Z
Outputs
O4–O7
L
H
Z
Outputs
O8–O11
L
H
Z
Inputs
Outputs
OE4
I12–I15
O12–O15
LL
L
LH
H
HX
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
Z
2
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74ALVC162244GX driver
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74ALVC162244GX
Low Voltage 16-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs and 26 Series Resistor in Outputs - Fairchild Semiconductor
