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74ACTQ827 반도체 회로 부품 판매점

Quiet Seriesa 10-Bit Buffer/Line Driver with 3-STATE Outputs



Fairchild Semiconductor 로고
Fairchild Semiconductor
74ACTQ827 데이터시트, 핀배열, 회로
March 1990
Revised December 1998
74ACTQ827
Quiet Series10-Bit Buffer/Line Driver
with 3-STATE Outputs
General Description
The ACTQ827 10-bit bus buffer provides high performance
bus interface buffering for wide data/address paths or
buses carrying parity. The 10-bit buffers have NOR output
enables for maximum control flexibility. The ACTQ827 uti-
lizes Fairchild Quiet Seriestechnology to guarantee quiet
output switching and improved dynamic threshold perfor-
mance. FACT Quiet Seriesfeatures GTOoutput control
and undershoot corrector in addition to a split ground bus
for superior performance.
Features
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance
s Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
s Improved latch-up immunity
s Outputs source/sink 24 mA
s Functionally and pin-compatible to AMD’s AM29827
s Has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74ACTQ827SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACTQ827SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment
for DIP and SOIC
IEEE/IEC
Pin Descriptions
Pin Names
OE1, OE2
D0–D9
O0–O9
Description
Output Enable
Data Inputs
Data Outputs
FACT, Quiet Series, FACT Quiet Seriesand GTOare trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010687.prf
www.fairchildsemi.com


74ACTQ827 데이터시트, 핀배열, 회로
Functional Description
The ACTQ827 line driver is designed to be employed as
memory address driver, clock driver and bus-oriented
transmitter/receiver. The devices have 3-STATE outputs
controlled by the Output Enable (OE) pins. When the OE is
LOW, the device is transparent. When OE is HIGH, the
device is in 3-STATE mode.
Function Table
Inputs Outputs Function
OE Dn
On
LH
H Transparent
LL
L Transparent
HX
Z High Z
H = HIGH Voltage Level
L = LOW Voltage Level
Z = HIGH Impedance
X = Immaterial
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
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74ACTQ827 driver

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