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Fairchild Semiconductor |
May 1991
Revised November 1999
74ACTQ16540
16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs
General Description
The ACTQ16540 contains sixteen inverting buffers with 3-
STATE outputs designed to be employed as a memory and
address driver, clock driver, or bus-oriented transmitter/
receiver. The device is byte controlled. Each byte has sep-
arate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The ACTQ16540 utilizes Fairchild Quiet Series technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series fea-
tures GTO output control for superior performance.
Features
s Utilizes Fairchild FACT Quiet Series technology
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin output skew
s Separate control logic for each byte
s Outputs source/sink 24 mA
s Additional specs for multiple output switching
s Output loading specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number Package Number
Package Description
74ACTQ16540SSC
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ACTQ16540MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin
Names
OEn
I0–I15
O0–O15
Description
Output Enable Input (Active LOW)
Inputs
Outputs
FACT, Quiet Series, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010927
www.fairchildsemi.com
Functional Description
The ACTQ16540 contains sixteen inverting buffers with 3-
STATE standard outputs. The device is byte controlled with
each byte functioning identically, but independent of the
other. The control pins may be shorted together to obtain
full 16-bit operation. The 3-STATE outputs are controlled by
an Output Enable (OEn) input for each byte. When OEn is
LOW, the outputs are in 2-state mode. When OEn is HIGH,
the outputs are in the high impedance mode, but this does
not interfere with entering new data into the inputs.
Logic Diagram
Truth Tables
Inputs
OE1
L
H
X
OE2
L
X
H
LL
Inputs
OE3
L
OE4
L
HX
XH
LL
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
I0–I7
H
X
X
L
I8–I15
H
X
X
L
Outputs
O0–O7
L
Z
Z
H
Outputs
O8–O15
L
Z
Z
H
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