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74ACT18825 반도체 회로 부품 판매점

18-Bit Buffer/Line Driver with 3-STATE Outputs



Fairchild Semiconductor 로고
Fairchild Semiconductor
74ACT18825 데이터시트, 핀배열, 회로
August 1999
Revised October 1999
74ACT18825
18-Bit Buffer/Line Driver with 3-STATE Outputs
General Description
The ACT18825 contains eighteen non-inverting buffers
with 3-STATE outputs designed to be employed as a mem-
ory and address driver, clock driver, or bus oriented trans-
mitter/receiver. The device is byte controlled. Each byte
has separate 3-STATE control inputs which can be shorted
together for full 18-bit operation.
Features
s Broadside pinout allows for easy board layout
s Separate control logic for each byte
s Extra data width for wider address/data paths or buses
carrying parity
s Outputs source/sink 24 mA
s TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74ACT18825SSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ACT18825MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
OEn
I0–I17
O0–O17
Description
Output Enable Input (Active LOW)
Inputs
Outputs
FACT, FACT Quiet Seriesand GTOare trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS0500292
www.fairchildsemi.com


74ACT18825 데이터시트, 핀배열, 회로
Functional Description
The ACT18825 contains eighteen non-inverting buffers
with 3-STATE standard outputs. The device is byte con-
trolled with each byte functioning identically, but indepen-
dently of the other. The control pins may be shorted
together to obtain full 8-bit operation. The 3-STATE outputs
are controlled by an Output Enable (OEn) input for each
byte. When OEn is LOW, the outputs are in 2-state mode.
When OEn is HIGH, the outputs are in the high impedance
mode, but this does not interfere with entering new data
into the inputs.
Truth Table
Inputs
Outputs
Byte 1 (0:8) Byte 2 (8:17)
I0–I8 I9–I17 O0–O8 O9–O17
OE1 OE2 OE3 OE4
LL L L HH
H
H
HX L L X L
Z
L
XH L L X H
Z
H
LLH X LX
L
Z
LLX HHX
H
Z
HH H H X X
Z
Z
LL L L L L
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = HIGH Impedance
Logic Diagram
www.fairchildsemi.com
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74ACT18825 driver

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