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Fairchild Semiconductor |
April 2001
Revised June 2003
FIN1027 • FIN1027A
3.3V LVDS 2-Bit High Speed Differential Driver
General Description
This dual driver is designed for high speed interconnects
utilizing Low Voltage Differential Signaling (LVDS) technol-
ogy. The driver translates LVTTL signal levels to LVDS lev-
els with a typical differential output swing of 350 mV which
provides low EMI at ultra low power dissipation even at
high frequencies. This device is ideal for high speed trans-
fer of clock or data.
The FIN1027 or FIN1027A can be paired with its compan-
ion receiver, the FIN1028, or with any other LVDS receiver.
Features
s Greater than 600Mbs data rate
s 3.3V power supply operation
s 0.5ns maximum differential pulse skew
s 1.5ns maximum propagation delay
s Low power dissipation
s Power-Off protection
s Meets or exceeds the TIA/EIA-644 LVDS standard
s Flow-through pinout simplifies PCB layout
s 8-Lead SOIC, US8, and 8-terminal MLP
packages save space
Ordering Code:
Order Number
FIN1027M
FIN1027MX
FIN1027K8X
FIN1027MPX
(Preliminary)
FIN1027AM
FIN1027AMX
Package Number
Package Description
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
[TUBE]
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
[TAPE and REEL]
MAB08A
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide
[TAPE and REEL]
MLP08C
8-Terminal Molded Leadless Package (MLP) Dual, JEDEC MO-229, 2mm Square
[TAPE and REEL]
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
[TUBE]
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
[TAPE and REEL]
© 2003 Fairchild Semiconductor Corporation DS500501
www.fairchildsemi.com
Connection Diagrams
Pin Assignments for SOIC
FIN1027
Pin Assignments for US8
for FIN1027
(Top View)
Pin Assignments for SOIC
FIN1027A
(Top View)
Terminal Assignments for MLP
FIN1027
(Top Through View)
(Top View)
Pin Descriptions
Pin Name
DIN1, DIN2
DOUT1+, DOUT2+
DOUT1−, DOUT2−
VCC
GND
Description
LVTTL Data Inputs
Non-inverting Driver Outputs
Inverting Driver Outputs
Power Supply
Ground
Function Table
Input
DIN
L
H
OPEN
H = HIGH Logic Level
L = LOW Logic Level
X = Don’t Care
Outputs
DOUT+
DOUT−
LH
HL
LH
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