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PDF AD8019 Data sheet ( Hoja de datos )
| Número de pieza | AD8019 | |
| Descripción | DSL Line Driver with Power-Down | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Low Distortion, High Output Current Amplifiers
Operate from 12 V to ؎12 V Power Supplies,
Ideal for High-Performance ADSL CPE, and xDSL
Modems
Low Power Operation
9 mA/Amp (Typ) Supply Current
Digital (1-Bit) Power-Down
Voltage Feedback Amplifiers
Low Distortion
Out-of-Band SFDR –80 dBc @ 100 kHz into 100 ⍀ Line
High Speed
175 MHz Bandwidth (–3 dB), G = +1
400 V/s Slew Rate
High Dynamic Range
VOUT to within 1.2 V of Power Supply
APPLICATIONS
ADSL, VDSL, HDSL, and Proprietary xDSL USB, PCI,
PCMCIA Modems, and Customer Premise Equipment
(CPE)
PRODUCT DESCRIPTION
The AD8019 is a low cost xDSL line driver optimized to drive a
minimum of 13 dBm into a 100 Ω load while delivering outstand-
ing distortion performance. The AD8019 is designed on a 24 V
high-speed bipolar process enabling the use of ± 12 V power
supplies or 12 V only. When operating from a single 12 V sup-
ply the highly efficient amplifier architecture can typically deliver
170 mA output current into low impedance loads through a
1:2 turns ratio transformer. Hybrid designs using ± 12 V supplies
enable the use of a 1:1 turns ratio transformer, minimizing attenu-
ation of the receive signal. The AD8019 typically draws 9 mA/
amplifier quiescent current. A 1-bit digital power down feature
reduces the quiescent current to approximately 1.6 mA/amplifier.
Figure 1 shows typical Out of Band SFDR performance under
ADSL CPE (upstream) conditions. SFDR is measured while
driving a 13 dBm ADSL DMT signal into a 100 Ω line with
50 Ω back termination.
The AD8019 comes in thermally enhanced 8-lead SOIC and
14-lead TSSOP packages. The 8-lead SOIC is pin-compatible
with the AD8017 12 V line driver.
DSL Line Driver
with Power-Down
AD8019
PIN CONFIGURATIONS
8-Lead SOIC
(R-8)
14-Lead TSSOP
(RU-14)
OUT1 1 AD8019AR 8 +VS
–IN1 2
7 OUT2
+IN1 3
6 –IN2
–VS 4
5 +IN2
NC 1
OUT1 2
–IN1 3
AD8019ARU 14 NC
13 +VS
12 OUT2
+IN1 4
11 –IN2
–VS 5
PWDN 6
10 +IN2
9 NC
NC 7
8 DGND
NC = NO CONNECT
–80dBc
132.5
137.5
FREQUENCY – kHz
142.5
Figure 1. Out-of-Band SFDR; VS = ±12 V; 13 dBm Output
Power into 200 Ω, Upstream
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
1 page  
Typical Performance Characteristics–AD8019
124⍀
499⍀
VOUT
RL
VIN
49.9⍀
+
0.1F 10F
+VS
+
0.1F 10F
–VS
TPC 1. Single-Ended Test Circuit; G = +5
+VS
+VIN
0.1F
+
47F
0.1F
–VIN
50⍀
500⍀
0.1F 55⍀
55⍀ 500⍀
50⍀
+VO
RL
–VO
–VS
TPC 4. Differential Test Circuit; G = +10
100
80
60
40
20
0
–20
–40
–60
–80
–100
–100
0
100 200 300 400 500 600 700
TIME – ns
TPC 2. 100 mV Step Response; G = +5, VS = ±6 V,
RL = 25 Ω, Single-Ended
4
3
2
1
0
–1
–2
–3
–4
–100
0
100 200 300 400 500 600 700
TIME – ns
TPC 3. 4 V Step Response; G = +5, VS = ±6 V,
RL = 25 Ω, Single-Ended
100
80
60
40
20
0
–20
–40
–60
–80
–100
–100
0
100 200 300 400 500 600 700
TIME – 100ns/DIV
TPC 5. 100 mV Step Response; G = +5, VS = ±12 V,
RL = 100 Ω, Single-Ended
4
3
2
1
0
–1
–2
–3
–4
–100
0
100 200 300 400 500 600 700
TIME – ns
TPC 6. 4 V Step Response; G = +5, VS = ±12 V,
RL = 100 Ω, Single-Ended
REV. 0
–5–
5 Page 
AD8019
GENERAL INFORMATION
The AD8019 is a voltage feedback amplifier with high output
current capability. As a voltage feedback amplifier, the AD8019
features lower current noise and more applications flexibility than
current feedback designs. It is fabricated on Analog Devices’
proprietary High Voltage eXtra Fast Complementary Bipolar
Process (XFCB-HV), which enables the construction of PNP
and NPN transistors with similar fTs in the 4 GHz region. The
process is dielectrically isolated to eliminate the parasitic and
latch-up problems caused by junction isolation. These features
enable the construction of high-frequency, low-distortion amplifiers.
POWER-DOWN FEATURE
A digitally programmable logic pin (PWDN) is available on the
TSSOP-14 package. It allows the user to select between two
operating conditions, full on and shutdown. The DGND pin is
the logic reference. The threshold for the PWDN pin is typically
1.8 V above DGND. If the power-down feature is not being
used, it is better to tie the DGND pin to the lowest potential
that the AD8019 is tied to and place the PWDN pin at a poten-
tial at least 3 V higher than that of the DGND pin, but lower
than the positive supply voltage.
POWER SUPPLY AND DECOUPLING
The AD8019 can be powered with a good quality (i.e., low-noise)
supply anywhere in the range from +12 V to ± 12 V. In order to
optimize the ADSL upstream drive capability of 13 dBm and
maintain the best Spurious Free Dynamic Range (SFDR), the
AD8019 circuit should be powered with a well-regulated supply.
Careful attention must be paid to decoupling the power supply.
High quality capacitors with low equivalent series resistance
(ESR) such as multilayer ceramic capacitors (MLCCs) should
be used to minimize supply voltage ripple and power dissipa-
tion. In addition, 0.1 µF MLCC decoupling capacitors should
be located no more than 1/8 inch away from each of the power
supply pins. A large, usually tantalum, 10 µF to 47 µF capacitor
is required to provide good decoupling for lower frequency
signals and to supply current for fast, large signal changes at
the AD8019 outputs.
POWER DISSIPATION
It is important to consider the total power dissipation of the
AD8019 in order to properly size the heat sink area of an appli-
cation. Figure 3 is a simple representation of a differential driver.
With some simplifying assumptions we can estimate the total
power dissipated in this circuit. If the output current is large
compared to the quiescent current, computing the dissipation
in the output devices and adding it to the quiescent power dissipa-
tion will give a close approximation of the total power dissipation in
the package. A factor α (~0.6-1) corrects for the slight error
due to the Class A/B operation of the output stage. It can be
estimated by subtracting the quiescent current in the output
stage from the total quiescent current and ratioing that to the
total quiescent current. For the AD8019, α = 0.833.
+VS
+VO
+VS
–VO
RL
–VS –VS
Figure 3. Simplified Differential Driver
Remembering that each output device only dissipates for half
the time gives a simple integral that computes the power for
each device:
1
2
∫
(VS
– VO ) ×
(2 VO )
RL
The total supply power can then be computed as:
PTOT
=
4
(VS
∫ |VO
|−
∫VO2
)
×
1
2
+
2
α
IQ
VS
+ POUT
In this differential driver, VO is the voltage at the output of one
amplifier, so 2 VO is the voltage across RL. RL is the total
impedance seen by the differential driver, including back
termination. Now, with two observations the integrals are easily
evaluated. First, the integral of VO2 is simply the square of the
rms value of VO. Second, the integral of | VO | is equal to the
average rectified value of VO, sometimes called the mean average
deviation, or MAD. It can be shown that for a DMT signal, the
MAD value is equal to 0.8 times the rms value.
PTOT
= 4 (0.8 VO
rms VS
– VO rms2 ) ×
1
RL
+2α
IQ VS
+ POUT
For the AD8019 operating on a single 12 V supply and delivering a
total of 16 dBm (13 dBm to the line and 3 dBm to the matching
network) into 17.3 Ω (100 Ω reflected back through a 1:1.7
transformer plus back termination), the dissipated power is:
= 332 mW + 40 mW
= 372 mW
Using these calculations and a θJA of 90°C/W for the TSSOP
package and 100°C/W for the SOIC, Tables I–IV show junc-
tion temperature versus power delivered to the line for several
supply voltages while operating with an ambient temperature
of 85°C. The shaded areas indicate operation at a junction
temperature over the absolute maximum rating of 150°C, and
should be avoided.
Table I. Junction Temperature vs. Line Power and Operating
Voltage for TSSOP
PLINE, dBm
13
14
15
16
17
18
؎12
132
134
136
139
141
143
VSUPPLY
؎12.5
134
137
139
141
144
147
؎13
137
139
141
144
147
150
REV. 0
–11–
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD8019.PDF ] | |
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