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AX2061 반도체 회로 부품 판매점

LCD Driver



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ON Semiconductor
AX2061 데이터시트, 핀배열, 회로
AX2061
LCD Driver for Low
Multiplex Rates
OVERVIEW
The AX2061 is an LCD driver for low multiplex rates. Figure 1
shows the block diagram of the AX2061. The chip is controlled by a
microcontroller using the SPI interface. The microcontroller writes
pixel (segment) data into the pixel data memory. Display updates may
be delayed using the pixel data latches. The pixel data latches drive the
segment drivers, while the row counter drives the row drivers.
Features
Singlechip LCD Controller/Driver 5 Row, 76 Segment Outputs
Wide Power Supply Range: from 2.2 V to 3.6 V
4bit Contrast Register
Selectable Row Drive Configuration: Static or 2/3/4/5 Row
Multiplexing
Internal Generation of LCD Bias Voltages with Charge Pump
from a Single 2.2 to 3.6 V Power Supply
76 × 5bit RAM for Display Data Storage
Autoincremented Display Data Loading
Low Power Consumption
Internal 32 kHz Oscillator
SPIBus Interface
BLOCK DIAGRAM
www.onsemi.com
ORDERING INFORMATION
Device
Package
Shipping
AX20611WD1 Wafer/Die Contact Sales
See additional information on page 16 of this data sheet.
VDD
ICLK
RREF
SYSCLK (32kHz)
optional
LATCH
VSS
SEL
CLK
MOSI
MISO
optional
CAP
Voltage Regulator / Pump
Oscillator
32 kHz
Frequency
Divider
Pixel
Address
Counter
SPI
Row Drivers
Frame
Counter
ROW#
ROW#
SEG#
Segment Drivers
Pixel Latches
Pixel Data Registers
Figure 1. Functional Block Diagram of the AX2061
© Semiconductor Components Industries, LLC, 2016
March, 2016 Rev. 3
1
Publication Order Number:
AX2061/D


AX2061 데이터시트, 핀배열, 회로
AX2061
Table 1. PIN FUNCTION DESCRIPTIONS
Symbol
Number of Pins Type
COM04
5A
SEG075
76 A
SEL 1 I
CLK 1 I
MISO
1O
MOSI
LATCH
1I
1 I/O
SYSCLK
1 I/O
ICLK
1 I/O
RREF
1A
VD1
VD2
VD3
VI
VDD
VDDCORE
CAPN
CAPP
VSS
TST
2A
2A
2A
2A
2P
2A
2A
2A
10 P
1N
Description
Row driver outputs
Segment driver outputs
SPI select
SPI clock
SPI data output
Can optionally be connected to read back register contents from the AX2061.
Reading registers is not required for the AX2061 functionality.
SPI data input
Latch pixel data into pixel latches
For alternative functionalities as well as required handling if not used see the
circuit description section
32 kHz clock input (default)
For alternative functionalities as well as required handling if not used see the
circuit description section
Internal 32 kHz clock output
For alternative functionalities as well as required handling if not used see the
circuit description section
Reference resistor for internal 32kHz oscillator
Connect 1 MW from RREF pin to VSS
Note that the reference resistor is required even if the internal 32 kHz oscillator is
not used to generate the framing clock
Decoupling output for internally generated LCD voltage VD1
Connect 100 nF capacitor from VD1 to VSS
Decoupling output for internally generated LCD voltage VD2
Connect 220 nF capacitor from VD2 to VSS
Decoupling output for internally generated LCD voltage VD3
Connect 100 nF capacitor from VD3 to VSS
Decoupling output for internal charge pump
Connect 1 mF capacitor from VI to VSS, note that voltage levels on this pin can
reach up to 5.2 V
Supply voltage input
Decoupling output for internally generated supply voltage for the core functionality
of the IC
Connect 1 mF capacitor from VDDCORE to VSS
Charge pump floating capacitor negative terminal
Connect 100 nF capacitor between CAPN and CAPP
Charge pump floating capacitor positive terminal
Connect 1 mF capacitor between CAPN and CAPP
Ground
Pin used for production testing, leave unconnected
Total
116
A = analog input
I = digital input signal
O = digital output signal
I/O = digital input/output signal
N = not to be connected
P = power or ground
All digital inputs are Schmitt trigger inputs, digital input
and output levels are LVCMOS/LVTTL compatible and 5 V
tolerant.
www.onsemi.com
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