74LVC2G125-Q100 반도체 회로 부품 판매점

Dual bus buffer/line driver



NXP Semiconductors 로고
NXP Semiconductors
74LVC2G125-Q100 데이터시트, 핀배열, 회로
74LVC2G125-Q100
Dual bus buffer/line driver; 3-state
Rev. 1 — 8 May 2013
Product data sheet
1. General description
The 74LVC2G125-Q100 provides a dual non-inverting buffer/line driver with 3-state
output. The output enable input (pin nOE) controls the 3-state output. A HIGH-level at pin
nOE causes the output to assume a high-impedance OFF-state. Schmitt trigger action at
all inputs makes the circuit highly tolerant of slower input rise and fall times.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
24 mA output drive (VCC = 3.0 V)
CMOS low-power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options

74LVC2G125-Q100 데이터시트, 핀배열, 회로
NXP Semiconductors
74LVC2G125-Q100
Dual bus buffer/line driver; 3-state
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74LVC2G125DP-Q100 40 C to +125 C TSSOP8
74LVC2G125DC-Q100 40 C to +125 C VSSOP8
Description
Version
plastic thin shrink small outline package; 8 leads; SOT505-2
body width 3 mm; lead length 0.5 mm
plastic very thin shrink small outline package;
8 leads; body width 2.3 mm
SOT765-1
4. Marking
Table 2. Marking codes
Type number
74LVC2G125DP-Q100
74LVC2G125DC-Q100
Marking code[1]
V25
V25
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
74LVC2G125
1A
1OE
2A
2OE
Fig 1. Logic symbol
1Y
2Y
mna941
74LVC2G125
1
EN1
2
EN2
001aae009
Fig 2. IEC logic symbol
74LVC2G125_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 May 2013
© NXP B.V. 2013. All rights reserved.
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74LVC2G125-Q100 driver

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Dual bus buffer/line driver - NXP Semiconductors