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PDF TM043NBH01 Data sheet ( Hoja de datos )
| Número de pieza | TM043NBH01 | |
| Descripción | Display Module | |
| Fabricantes | Tianma | |
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SHANGHAI TIANMA MICRO-ELECTRONICS
TM043NBH01 V1.7
MODEL NO. :
ISSUED DATE:
VERSION :
TM043NBH01
2011-03-18
Ver 1.7
□Preliminary Specification
■Final Product Specification
Customer :
Approved by
Notes
SHANGHAI TIANMA Confirmed :
This technical specification is subjected to change without notice
The information contained herein is the exclusive property of SHANGHAI TIANMA MICRO-ELECTRONICS
Corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written
permission of SHANGHAI TIANMA MICRO-ELECTRONICS Corporation.
Page 1 of 21
1 page  
SHANGHAI TIANMA MICRO-ELECTRONICS
2 Input/Output Terminals
2.1 TFT LCD Panel
TM043NBH01 V1.7
NO Symbol I/O Description
Comment
1 VSS
P Ground
2 VSS
P Ground
3 VDD
P Power supply
4 VDD
P Power supply
5 R0
I Data input
6 R1
I Data input
7 R2
I Data input
8 R3
I Data input
9 R4
I Data input
10 R5
I Data input
11 R6
I Data input
12 R7
I Data input
13 G0
I Data input
14 G1
I Data input
15 G2
I Data input
16 G3
I Data input
17 G4
I Data input
18 G5
I Data input
19 G6
I Data input
20 G7
I Data input
21 B0
I Data input
22 B1
I Data input
23 B2
I Data input
24 B3
I Data input
25 B4
I Data input
26 B5
I Data input
27 B6
I Data input
28 B7
I Data input
29 VSS
P Ground
30 PCLK
I
Clock for input data. Data is latched at falling edge
of this signal.
Standby mode.
31 PON
I PON =“1”: Normally operation.
PON =“0”: Standby mode.
32 HSYNC
I
Horizontal sync input with negative polarity. If
unused, please pull high level.
33 VSYNC
I
Vertical sync input with negative polarity. If unused,
please pull high level.
34 DE
I Data input enable. If unused, please pull low level.
35 PWRSEL —— No connection
36 VSS
P Ground
37 Y2
—— YU
38 X2
—— XL
The information contained herein is the exclusive property of SHANGHAI TIANMA MICRO-ELECTRONICS
Corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written
permission of SHANGHAI TIANMA MICRO-ELECTRONICS Corporation.
Page 5 of 21
5 Page 
SHANGHAI TIANMA MICRO-ELECTRONICS
5.2 Input Setup Timing Parameter Setting
Parameter
Symbol Min Typ Max
DCLK Cycle Time
Tpw 66.7
-
-
DCLK Pulse High Width
Tpwh
26.7
-
-
DCLK Pulse Low Width
Tpwl 26.7
-
-
DE Setup Time
Tdes
10
-
-
DE Hold Time
Tdeh
10
-
-
HSYNC Setup Time
Ths 10
-
-
HSYNC Hold Time
Thh 10
-
-
VSYNC Setup Time
Tvhs 10
-
-
VSYNC Hold Time
Tvhh
10
-
-
Data Setup Time
Tds 10
-
-
Data Hold Time
Tdh 10
-
-
PON Setup Time
Tdiss
10
-
-
PON Hold Time
Tdish
10
-
-
Note 1: tr=tf=2ns.tr, tf is defined 10% to 90% of signal amplitude.
Note 2: For parallel interface, maximum clock frequency is 15MHz.
Note 3: Input time lager than Min value is in spec.
TM043NBH01 V1.7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VDD=3.3V Ta=25℃
Remark
The information contained herein is the exclusive property of SHANGHAI TIANMA MICRO-ELECTRONICS
Corporation, and shall not be distributed, reproduced, or disclosed in whole or in part without prior written
permission of SHANGHAI TIANMA MICRO-ELECTRONICS Corporation.
Page 11 of 21
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet TM043NBH01.PDF ] | |
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