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Linear Integrated Systems |
Linear Integrated Systems
ID100 ID101
MONOLITHIC DUAL
PICO AMPERE DIODES
FEATURES
DIRECT REPLACEMENT FOR INTERSIL ID100 & ID101
REVERSE LEAKAGE CURRENT
REVERSE BREAKDOWN VOLTAGE
REVERSE CAPACITANCE
ABSOLUTE MAXIMUM RATINGS1
IR = 0.1pA
BVR ≥ 30V
Crss = 0.75pF
@ 25 °C (unless otherwise stated)
Maximum Temperatures
Storage Temperature
-65 to +200 °C
Operating Junction Temperature
-55 to +150 °C
Maximum Power Dissipation
Continuous Power Dissipation
300mW
Maximum Currents
Forward Current
20mA
Reverse Current
100µA
Maximum Voltages
Reverse Voltage
30V
Diode to Diode Voltage
±50V
ID100
TO-78
BOTTOM VIEW
ID101
TO-71
BOTTOM VIEW
NC 3
A1 2
K1 1
5 NC
6 A2
7 K2
NC 3
A1 2
K1 1
5 NC
6 A2
7 K2
ELECTRICAL CHARACTERISTICS @ 25 °C (unless otherwise stated)
SYMBOL CHARACTERISTIC
MIN TYP MAX
BVR Reverse Breakdown Voltage
VF Forward Voltage
30
0.8 1.1
IR Reverse Leakage Current
0.1
2.0 10
|IR1-IR2|
Crss
Differential Leakage Current
Total Reverse Capacitance2
3
0.75 1
UNITS
V
pA
pF
CONDITIONS
IR = 1µA
IF = 10mA
VR = 1V
VR = 10V
VR = 10V, f = 1MHz
Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261
Figure 1. Operational Amplifier Protection
Input Differential Voltage limited to 0.8V (typ) by Diodes ID100 D1 and D2.
Common Mode Input voltage limited by Diodes ID100 D3 and D4 to ±15V.
Figure 2. Sample and Hold Circuit
Typical Sample and Hold circuit with clipping. ID100 diodes reduce offset
voltages fed capacitively from the ID100 switch gate.
FIGURE 1
FIGURE 2
ID100
-
D1 D2 OP-27
+
D3 D4
+15V -15V
ein CONTROL
SIGNAL
+V -V
ID100
D1
D2
2N4393
C
+V
2N4117A
R VOUT
TO-78
0.016
0.019
DIM. A
0.335
0.370
0.305
0.335
MAX.
0.040 0.165
0.185
MIN. 0.500
0.016
0.021
DIM. B
0.029
0.045
0.200
SEATING
PLANE
0.100
23
15
76
0.100
45°
0.028
0.034
TO-71
Six Lead
0.195 DIA.
0.175
0.030
MAX.
0.230 DIA.
0.209
0.150
0.115
6 LEADS
0.019 DIA.
0.016
0.500 MIN.
0.100
0.050
23
15
6
45° 7
0.046
0.036
0.048
0.028
1. Absolute maximum ratings are limiting values above which serviceability may be impaired.
2. Design reference only, not 100% tested.
3. Pins 3 & 5 on ID100 and ID101 must not be connected, in any fashion or manner, to any circuit or node.
Information furnished by Linear Integrated Systems is believed to be accurate and reliable. However, no responsibility is assumed for its
use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Linear Integrated Systems.
Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261
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