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ADF4355-2 반도체 회로 부품 판매점

Microwave Wideband Synthesizer



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Analog Devices
ADF4355-2 데이터시트, 핀배열, 회로
Data Sheet
Microwave Wideband Synthesizer
with Integrated VCO
ADF4355-2
FEATURES
GENERAL DESCRIPTION
RF output frequency range: 54 MHz to 4400 MHz
The ADF4355-2 allows implementation of fractional-N or
Fractional-N synthesizer and integer-N synthesizer
integer-N phase-locked loop (PLL) frequency synthesizers
High resolution 38-bit modulus
when used with an external loop filter and an external reference
Low phase noise, VCO
Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output
Analog and digital power supplies: 3.3 V
Charge pump and VCO power supplies: 5 V typical
Logic compatibility: 1.8 V
Programmable dual modulus prescaler of 4/5 or 8/9
Programmable output power level
RF output mute function
3-wire serial interface
Analog and digital lock detect
APPLICATIONS
frequency. A series of frequency dividers permits operation
from 54 MHz to 4400 MHz.
The ADF4355-2 has an integrated voltage controlled oscillator
(VCO) with a fundamental output frequency ranging from
3400 MHz to 6800 MHz. In addition, the VCO frequency is
connected to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allow
the user to generate radio frequency (RF) output frequencies as
low as 54 MHz. For applications that require isolation, the RF
output stage can be muted. The mute function is both pin and
software controllable.
Control of all on-chip registers is through a simple 3-wire interface.
Wireless infrastructure (W-CDMA, TD-SCDMA,
The ADF4355-2 operates with analog and digital power supplies,
WiMAX, GSM, PCS, DCS, DECT)
Point to point/point to multipoint microwave links
Satellites/VSATs
Test equipment/instrumentation
ranging from 3.15 V to 3.45 V, with charge pump and VCO
supplies from 4.75 V to 5.25 V. The ADF4355-2 also contains
hardware and software power-down modes.
Clock generation
FUNCTIONAL BLOCK DIAGRAM
CE
AVDD
DVDD
VP
RSET
VVCO
VRF
AVDD
REFINA
REFIN B
CLK
DATA
LE
×2
DOUBLER
10-BIT R
COUNTER
÷2
DIVIDER
DATA REGISTER
FUNCTION
LATCH
INTEGER
REG
FRACTION MODULUS
REG
REG
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
LOCK
DETECT
MULTIPLEXER
CHARGE
PUMP
PHASE
COMPARATOR
VCO
CORE
÷11/62/3/42//864
N COUNTER
AGND
CPGND
AGNDRF
Figure 1.
MULTIPLEXER
SDGND AGNDVCO
OUTPUT
STAGE
OUTPUT
STAGE
MUXOUT
CREG1
CREG2
CPOUT
VTUNE
VREF
VBIAS
VREGVCO
RFOUTA+
RFOUTA–
PDBRF
RFOUTB+
RFOUTB–
ADF4355-2
Rev. B
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700 ©2014–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com


ADF4355-2 데이터시트, 핀배열, 회로
ADF4355-2
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings............................................................ 7
Transistor Count........................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... 10
Circuit Description......................................................................... 13
Reference Input Section............................................................. 13
RF N Divider............................................................................... 13
Phase Frequency Detector (PFD) and Charge Pump............ 14
MUXOUT and Lock Detect...................................................... 14
Input Shift Registers ................................................................... 14
Program Modes .......................................................................... 15
VCO.............................................................................................. 15
Output Stage................................................................................ 15
Register Maps .................................................................................. 17
Register 0 ..................................................................................... 19
Register 1 ..................................................................................... 20
Register 2 ..................................................................................... 21
Register 3 ..................................................................................... 22
Data Sheet
Register 4 ..................................................................................... 23
Register 5 ..................................................................................... 24
Register 6 ..................................................................................... 25
Register 7 ..................................................................................... 27
Register 8 ..................................................................................... 28
Register 9 ..................................................................................... 28
Register 10 ................................................................................... 29
Register 11 ................................................................................... 29
Register 12 ................................................................................... 30
Register Initialization Sequence ............................................... 30
Frequency Update Sequence..................................................... 31
RF Synthesizer—A Worked Example ...................................... 31
Reference Doubler and Reference Divider ............................. 32
Spurious Optimization and Fast Lock..................................... 32
Optimizing Jitter......................................................................... 32
Spur Mechanisms ....................................................................... 32
Lock Time.................................................................................... 32
Applications Information .............................................................. 34
Direct Conversion Modulator .................................................. 34
Printed Circuit Board (PCB) Design Guidelines for a Chip-
Scale Package .............................................................................. 35
Output Matching ........................................................................ 36
Outline Dimensions ....................................................................... 37
Ordering Guide .......................................................................... 37
Rev. B | Page 2 of 37




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