W631GG8KB 반도체 회로 부품 판매점
16M x 8-BANKS x 8-BIT DDR3 SDRAM
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 Winbond |
W631GG8KB
16M 8 BANKS 8 BIT DDR3 SDRAM
Table of Contents-
1. GENERAL DESCRIPTION ...................................................................................................................5
2. FEATURES ...........................................................................................................................................5
3. ORDER INFORMATION .......................................................................................................................6
4. KEY PARAMETERS .............................................................................................................................7
5. BALL CONFIGURATION ......................................................................................................................8
6. BALL DESCRIPTION............................................................................................................................9
7. BLOCK DIAGRAM ..............................................................................................................................11
8. FUNCTIONAL DESCRIPTION............................................................................................................12
8.1 Basic Functionality ..............................................................................................................................12
8.2 RESET and Initialization Procedure ....................................................................................................12
8.2.1
Power-up Initialization Sequence .....................................................................................12
8.2.2
Reset Initialization with Stable Power ..............................................................................14
8.3 Programming the Mode Registers.......................................................................................................15
8.3.1
Mode Register MR0 .........................................................................................................17
8.3.1.1
Burst Length, Type and Order ................................................................................17
8.3.1.2
CAS Latency...........................................................................................................18
8.3.1.3
Test Mode...............................................................................................................18
8.3.1.4
DLL Reset...............................................................................................................18
8.3.1.5
Write Recovery .......................................................................................................19
8.3.1.6
Precharge PD DLL .................................................................................................19
8.3.2
Mode Register MR1 .........................................................................................................19
8.3.2.1
DLL Enable/Disable................................................................................................20
8.3.2.2
Output Driver Impedance Control ...........................................................................20
8.3.2.3
ODT RTT Values ....................................................................................................20
8.3.2.4
Additive Latency (AL) .............................................................................................20
8.3.2.5
Write leveling ..........................................................................................................20
8.3.2.6
Output Disable........................................................................................................21
8.3.2.7
TDQS, TDQS#........................................................................................................21
8.3.3
Mode Register MR2 .........................................................................................................22
8.3.3.1
Partial Array Self Refresh (PASR) ..........................................................................23
8.3.3.2
CAS Write Latency (CWL) ......................................................................................23
8.3.3.3
Auto Self Refresh (ASR) and Self Refresh Temperature (SRT) .............................23
8.3.3.4
Dynamic ODT (Rtt_WR) .........................................................................................23
8.3.4
Mode Register MR3 .........................................................................................................24
8.3.4.1
Multi Purpose Register (MPR) ................................................................................24
8.4 No OPeration (NOP) Command..........................................................................................................25
8.5 Deselect Command.............................................................................................................................25
8.6 DLL-off Mode ......................................................................................................................................25
8.7 DLL on/off switching procedure...........................................................................................................26
8.7.1
DLL “on” to DLL “off” Procedure ..........................................................................26
8.7.2
DLL “off” to DLL “on” Procedure ..........................................................................27
8.8 Input clock frequency change..............................................................................................................28
8.8.1
Frequency change during Self-Refresh............................................................................28
8.8.2
Frequency change during Precharge Power-down ..........................................................28
Publication Release Date: Dec. 08, 2014
Revision: A04
-1-
W631GG8KB
8.9 Write Leveling .....................................................................................................................................30
8.9.1
DRAM setting for write leveling & DRAM termination function in that mode ....................31
8.9.2
Write Leveling Procedure.................................................................................................31
8.9.3
Write Leveling Mode Exit .................................................................................................33
8.10 Multi Purpose Register........................................................................................................................34
8.10.1
MPR Functional Description.............................................................................................35
8.10.2
MPR Register Address Definition.....................................................................................36
8.10.3
Relevant Timing Parameters............................................................................................36
8.10.4
Protocol Example .............................................................................................................36
8.11 ACTIVE Command..............................................................................................................................42
8.12 PRECHARGE Command ....................................................................................................................42
8.13 READ Operation .................................................................................................................................43
8.13.1
READ Burst Operation .....................................................................................................43
8.13.2
READ Timing Definitions..................................................................................................44
8.13.2.1
READ Timing; Clock to Data Strobe relationship....................................................45
8.13.2.2
READ Timing; Data Strobe to Data relationship .....................................................46
8.13.2.3
tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation .............................................47
8.13.2.4
tRPRE Calculation..................................................................................................48
8.13.2.5
tRPST Calculation ..................................................................................................48
8.13.2.6
Burst Read Operation followed by a Precharge......................................................54
8.14 WRITE Operation................................................................................................................................56
8.14.1
DDR3 Burst Operation .....................................................................................................56
8.14.2
WRITE Timing Violations .................................................................................................56
8.14.2.1
Motivation ...............................................................................................................56
8.14.2.2
Data Setup and Hold Violations..............................................................................56
8.14.2.3
Strobe to Strobe and Strobe to Clock Violations.....................................................56
8.14.2.4
Write Timing Parameters ........................................................................................56
8.14.3
Write Data Mask...............................................................................................................57
8.14.4
tWPRE Calculation...........................................................................................................58
8.14.5
tWPST Calculation ...........................................................................................................58
8.15 Refresh Command ..............................................................................................................................65
8.16 Self-Refresh Operation .......................................................................................................................67
8.17 Power-Down Modes............................................................................................................................69
8.17.1
Power-Down Entry and Exit .............................................................................................69
8.17.2
Power-Down clarifications - Case 1 .................................................................................75
8.17.3
Power-Down clarifications - Case 2 .................................................................................75
8.17.4
Power-Down clarifications - Case 3 .................................................................................76
8.18 ZQ Calibration Commands..................................................................................................................77
8.18.1
ZQ Calibration Description ...............................................................................................77
8.18.2
ZQ Calibration Timing ......................................................................................................78
8.18.3
ZQ External Resistor Value, Tolerance, and Capacitive loading......................................78
8.19 On-Die Termination (ODT) ..................................................................................................................79
8.19.1
ODT Mode Register and ODT Truth Table ......................................................................79
8.19.2
Synchronous ODT Mode..................................................................................................80
8.19.2.1
ODT Latency and Posted ODT...............................................................................80
8.19.2.2
Timing Parameters .................................................................................................80
8.19.2.3
ODT during Reads..................................................................................................82
8.19.3
Dynamic ODT ..................................................................................................................83
8.19.3.1
Functional Description: ...........................................................................................83
Publication Release Date: Dec. 08, 2014
Revision: A04
-2-
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