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STMicroelectronics |
VX6854LC
QXGA EDOF camera module
Datasheet - production data
Description
The VX6854LC 3 megapixel camera module is
designed to be used for high quality still camera
function and also supports video modes. The
camera silicon device is SMIA 1.0 profile 2
compliant and is capable of generating raw bayer
3 Mpixel images up to 20 fps. The VX6854LC
supports the CCI control and CCP 2.0 and CSI-2
data interfaces.
The module design is optimized for both footprint
and height. The module provides excellent image
quality at focus distances from less than 50 cm to
infinity.
Features
• 3.15 megapixel resolution sensor (2048 x1536)
• Extended Depth of Field (EDOF)
• Compact size: 6.5 x 6.5 x 4.6mm
• SMIA Profile 2 compliant
• MIPI(a) CSI-2 (v0.9 D-PHY) and SMIA CCP2
video data interface
• CCI command interface 100 KHz up to
400 KHz
• 2.8V (analog) / 1.8V (digital) operation
• Integral EMC shielding
• Binning mode (2x2)
• Defect correction
• 4-channel lens shading correction
VX6854LC offers an ultra low power consumption
hardware standby mode consuming less than
50 μW (typical).
A separate hardware accelerator (STV0987)
device can be incorporated in the phone system
to run the associated image processing
algorithms in hardware where the baseband
cannot support this processing load.
Table 1. Device summary
Order code
Package
Packing
VX6854LCQ05I/1 SMIA65 Tape and reel
a. Copyright MIPI alliance standard for camera serial
interface 2v1.0 and MIPI alliance specification D-PHY
v 0.9
September 2015
This is information on a product in full production.
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1/114
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Contents
Contents
VX6854LC
1
2
3
4
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Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1 VX6854LC use in system with hardware co-processor . . . . . . . . . . . . . . 13
1.2 VX6854LC use in system with software image processing . . . . . . . . . . . 14
1.3 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Device pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 ESD protection diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 Analog video block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 Digital video block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.2 Dark calibration algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3 Device operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4.1 Power-up procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.2 Power-down procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4.3 Internal power-on reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4.4 Failsafe signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5 Clock and frame rate timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5.1 Video frame rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5.2 PLL and clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5.3 Clock input type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.6 Control and video interface formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.6.1 CCP/CSI-2 serial data link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.6.2 CCI serial control bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1 Status registers [0x0000 to 0x000F] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.2 Frame format description registers [0x0040 to 0x007F] . . . . . . . . . . . . . . 31
4.3 Analogue gain description registers [0x0080 to 0x0097] . . . . . . . . . . . . . 31
4.4 Data format description registers [0x00C0 to 0x00FF] . . . . . . . . . . . . . . . 32
4.5 Setup registers [0x0100 to 0x01FF] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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