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R5F364A6NFA 데이터시트, 핀배열, 회로
Datasheet
M16C/64A Group
RENESAS MCU
R01DS0032EJ0200
Rev.2.00
Feb 07, 2011
1. Overview
1.1 Features
The M16C/64A Group microcomputer (MCU) incorporates the M16C/60 Series CPU core and flash
memory, employing sophisticated instructions for a high level of efficiency. This MCU has 1 MB of address
space (expandable to 4 MB), and it is capable of executing instructions at high speed. In addition, the
CPU core boasts a multiplier for high-speed operation processing.
This MCU consumes low power, and supports operating modes that allow additional power control. The
MCU also uses an anti-noise configuration to reduce emissions of electromagnetic noise and is designed
to withstand electromagnetic interference (EMI). By integrating many of the peripheral functions, including
the multifunction timer and serial interface, the number of system components has been reduced.
1.1.1 Applications
This MCU can be used in audio components, cameras, televisions, household appliances, office
equipment, communication devices, mobile devices, industrial equipment, and other applications.
R01DS0032EJ0200 Rev.2.00
Feb 07, 2011
Page 1 of 88


R5F364A6NFA 데이터시트, 핀배열, 회로
M16C/64A Group
1. Overview
1.2 Specifications
The M16C/64A Group includes 100-pin package. Table 1.1 and Table 1.2 list specifications.
Table 1.1 Specifications for the 100-Pin Package (1/2)
Item Function
Description
CPU
Central processing unit
M16C/60 Series core
(multiplier: 16 bit × 16 bit  32 bit,
multiply and accumulate instruction: 16 bit × 16 bit + 32 bit  32 bit)
Number of basic instructions: 91
Minimum instruction execution time:
40.0 ns (f(BCLK) = 25 MHz, VCC1 = VCC2 = 2.7 to 5.5 V)
Operating modes: Single-chip, memory expansion, and microprocessor
Memory
ROM, RAM, data flash
See Table 1.3 “Product List”.
Voltage
Detection
Voltage detector
Power-on reset
3 voltage detection points (detection level of voltage detection 0 and 1
selectable)
Clock
Clock generator
4 circuits: Main clock, sub clock, low-speed on-chip oscillator (125 kHz),
PLL frequency synthesizer
Oscillation stop detection: Main clock oscillation stop/restart detection
function
Frequency divider circuit: Divide ratio selectable from 1, 2, 4, 8, and 16
Power saving features: Wait mode, stop mode
Real-time clock
External Bus
Expansion
Bus memory expansion
Address space: 1 MB
External bus interface: 0 to 3 waits inserted, 4 chip select outputs,
memory area expansion function (expandable to 4 MB), 3 V and 5 V
interfaces
Bus format: Separate bus or multiplexed bus selectable, data bus width
selectable (8 or 16 bits), number of address buses selectable (12, 16, or
20)
I/O Ports
Programmable I/O ports
CMOS I/O ports: 85 (selectable pull-up resistors)
N-channel open drain ports: 3
Interrupts
Interrupt vectors: 70
External interrupt inputs: 13 (NMI, INT × 8, key input × 4)
Interrupt priority levels: 7
Watchdog Timer
15-bit timer × 1 (with prescaler)
Automatic reset start function selectable
DMA
DMAC
4 channels, cycle steal mode
Trigger sources: 43
Transfer modes: 2 (single transfer, repeat transfer)
R01DS0032EJ0200 Rev.2.00
Feb 07, 2011
Page 2 of 88




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